LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 969
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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42.2.6.8 Set status register
Table 912. Interrupt clear status register (CLR_STAT - address 0x4004 4FE8) bit description
Table 913. Interrupt set status register (SET_STAT - address 0x4004 4FEC) bit description
Bit
18:17
19
31:20
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
WAKEUP0_SETST
WAKEUP1_SETST
WAKEUP2_SETST
WAKEUP3_SETST
ATIMER_SETST
RTC_SETST
BOD_SETST
WWDT_SETST
ETH_SETST
USB0_SETST
USB1_SETST
-
CAN_SETST
TIM2_SETST
TIM6_SETST
QEI_SETST
TIM14_SETST
Symbol
-
RESET_CLRST
-
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Writing a 1 to this bit sets the STATUS event bit 0 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 1 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 2 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 3 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 4 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 5 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 6 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 7 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 8 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 9 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 10 in the
STATUS register.
Reserved.
Writing a 1 to this bit sets the STATUS event bit 12 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 13 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 14 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 15 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 16 in the
STATUS register.
Description
Writing a 1 to this bit clears the STATUS event bit 19 in
the STATUS register.
Reserved.
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
969 of 1164
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Reset
value
Reset
value
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