LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 93

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
9.7.4.3.3 Mode 1b: Normal operating mode with post-divider and without pre-divider
9.7.4.3.4 Mode 1c: Normal operating mode without post-divider and with pre-divider
9.7.4.3.5 Mode 1d: Normal operating mode with post-divider and with pre-divider
9.7.4.3.6 Mode 3: Power down mode (pd)
9.7.4.4 Settings for USB0
Fout = Fcco = 2 x M x Fin (275 MHz Fcco 550 MHz, 4 kHz  Fin 150 MHz)
The feedback divider ratio is programmable:
In normal operating mode 1b the pre-divider is bypassed. The operating frequencies are:
Fout = Fcco /(2 x P) = (M / P) x Fin  (275 MHz Fcco 550 MHz, 4 kHz Fin  150 MHz)
The divider ratios are programmable:
In normal operating mode 1c the post-divider with divide-by-2 divider is bypassed. The
operating frequencies are:
Fout = Fcco = 2 x M x Fin / N  (275 MHz Fcco 550 MHz, 4 kHz Fin/N 150 MHz)
The divider ratios are programmable:
In normal operating mode 1d none of the dividers are bypassed. The operating
frequencies are:
Fout = Fcco /(2 x P) = M x Fin /(N x P)  (275 MHz Fcco 550 MHz, 4 kHz Fin/N 150
MHz)
The divider ratios are programmable:
In this mode (pd = '1'), the oscillator will be stopped, the lock output will be made low, and
the internal current reference will be turned off. During pd it is also possible to load new
divider ratios at the input buses (msel, psel, nsel). Power-down mode is ended by making
pd low, causing the PLL to start up. The lock signal will be made high once the PLL has
regained lock on the input clock.
Table 74
USB0.
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•
•
•
•
•
•
•
Feedback-divider M (M, 1 to 2
Feedback-divider M (M, 1 to 2
Post-divider P (P, 1 to 32)
Pre-divider N (N, 1 to 256)
Feedback-divider M (M, 1 to 2
Pre-divider N (N, 1 to 256)
Feedback-divider M (M, 1 to 2
Post-divider P (P, 1 to 32)
shows the divider settings used for configuring a certain output frequency F
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
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Chapter 9: LPC18xx Clock Generation Unit (CGU)
UM10430
© NXP B.V. 2011. All rights reserved.
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