LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 689

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
29.4 Register description
<Document ID>
User manual
29.4.1 Downcounter register
29.4.2 Preset value register
29.4.3 Interrupt clear enable register
Table 612. Register overview: Alarm timer (base address 0x4004 0000)
Table 613. Downcounter register (DOWNCOUNTER - 0x4004 0000) bit description
Table 614. Preset value register (PRESET - 0x4004 0004) bit description
Table 615. Interrupt clear enable register (CLR_EN - 0x4004 0FD8) bit description
Name
DOWNCOUNTER
PRESET
-
CLR_EN
SET_EN
STATUS
ENABLE
CLR_STAT
SET_STAT
Bit
15:0
31:16
Bit
15:0
31:16
Bit
0
31:1
Symbol
CVAL
-
Symbol
PRESETVAL
-
Symbol
CLR_EN
-
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R/W
R/W
W
W
R
W
W
Access
-
R
Description
When equal to zero an interrupt is raised.
When equal to zero PRESET is loaded and counting
continues.
Reserved.
Description
Writing a 1 to this bit clears the interrupt enable bit in the
ENABLE register.
Reserved.
Rev. 00.13 — 20 July 2011
Description
Value loaded in DOWNCOUNTER when
DOWNCOUNTER equals zero
Reserved.
Address
offset
0x000
0x004
0x008 -
0xFD4
0xFD8
0xFDC
0xFE0
0xFE4
0xFE8
0xFEC
Description
Downcounter register
Preset value register
Reserved
Interrupt clear enable register
Interrupt set enable register
Status register
Enable register
Clear register
Set register
Chapter 29: LPC18xx Alarm timer
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0x0
-
Reset value
-
Reset value
-
-
Reset
Value
0x000
0x000
-
0x0
0x0
0x0
0x0
0x0
0x0
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