LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 556
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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23.6.12 Upper Panel Current Address register
23.6.13 Lower Panel Current Address register
Table 466. Interrupt Clear register (INTCLR, address 0x4000 8028) bit description
The UPCURR register is Read-Only, and contains an approximate value of the upper
panel data DMA address when read.
Note: This register can change at any time and therefore can only be used as a rough
indication of display position.
The contents of the UPCURR register are described in
Table 467. Upper Panel Current Address register (UPCURR, address 0x4000 802C) bit
The LPCURR register is Read-Only, and contains an approximate value of the lower
panel data DMA address when read.
Note: This register can change at any time and therefore can only be used as a rough
indication of display position.
Table 468. Lower Panel Current Address register (LPCURR, address 0x4000 8030) bit
Bits
0
1
2
3
4
31:5
Bits
31:0
Bits
31:0
Function
-
FUFIC
LNBUIC
VCOMPIC
BERIC
-
Function
LCDUPCURR LCD Upper Panel Current Address.
Function
LCDLPCURR
description
description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
FIFO underflow interrupt clear.
Writing a 1 to this bit clears the FIFO underflow interrupt.
LCD next address base update interrupt clear.
Writing a 1 to this bit clears the LCD next address base update
interrupt.
Vertical compare interrupt clear.
Writing a 1 to this bit clears the vertical compare interrupt.
AHB master error interrupt clear.
Writing a 1 to this bit clears the AHB master error interrupt.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
Contains the current LCD upper panel data DMA address.
Description
LCD Lower Panel Current Address.
Contains the current LCD lower panel data DMA address.
Table
467.
Chapter 23: LPC18xx LCD
UM10430
© NXP B.V. 2011. All rights reserved.
556 of 1164
Reset
value
-
0x0
0x0
0x0
0x0
-
Reset
value
0x0
Reset
value
0x0
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