LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 564

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
Fig 53. LCD controller block diagram
23.7.1.1 AMBA AHB slave interface
23.7.1.2 AMBA AHB master interface
23.7.1 AHB interfaces
interface
interface
master
slave
AHB
AHB
The LCD controller includes two separate AHB interfaces. The first, an AHB slave
interface, is used primarily by the CPU to access control and data registers within the LCD
controller. The second, an AHB master interface, is used by the LCD controller for DMA
access to display data stored in memory elsewhere in the system. The LCD DMA
controller can access any SRAM on AHB and the external memory.
The AHB slave interface connects the LCD controller to the AHB bus and provides CPU
accesses to the registers and palette RAM.
The AHB master interface transfers display data from a selected slave (memory) to the
LCD controller DMA FIFOs. It can be configured to obtain data from any on-chip SRAM on
AHB, various types of off-chip static memory, or off-chip SDRAM.
control
Upper
Lower
panel
panel
FIFO
FIFO
FIFO
Input
DMA
DMA
All information provided in this document is subject to legal disclaimers.
serializer
Pixel
Rev. 00.13 — 20 July 2011
Hardware
(128x32)
palette
Cursor
RAM
FIFO underflow
AHB error
scaler
Gray
formatter
formatter
Upper
Lower
panel
panel
Panel clock
generator
controller
Timing
generation
Chapter 23: LPC18xx LCD
STN/TFT
Interrupt
select
data
Upper
output
Lower
output
panel
panel
FIFO
FIFO
UM10430
LCD control
LCDCLKIN
LCD panel
LCD panel
© NXP B.V. 2011. All rights reserved.
signals
Interrupt
clock
Upper
Lower
STN
STN
data
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