LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 1003

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
42.4.8.1 Programming the CGU for Deep-sleep and Power-down modes
42.4.8 Example CGU configurations
Non-integer mode
In this mode the post-divider is enabled and the feedback divider is set to run directly on
the CCO clock, which gives the following frequency dividers:
Direct mode
In this mode, the post-divider is disabled and the CCO clock is sent directly to the output,
leading to the following frequency equation:
Power-down mode
In this mode, the internal current reference will be turned off, the oscillator and the
phase-frequency detector will be stopped and the dividers will enter a reset state. While in
Power-down mode, the lock output will be low, to indicate that the PLL is not in lock. When
the Power-down mode is terminated, the PLL will resume its normal operation and will
make the lock signal high once it has regained lock on the input clock.
Before the LPC18xx enters Deep-sleep or Power-down mode, the IRC must be
programmed as the clock source in the control registers for all output stages (OUTCLK_0
to OUTCLK_20). In addition, the PLLs must be in Power-down mode.
All information provided in this document is subject to legal disclaimers.
FCCO
Rev. 00.13 — 20 July 2011
FCLKOUT
FCLKOUT
=
2

P
FCCO

FCLKOUT
=
=
FCCO
---------------- -
2
FCCO
=

P
M

=
FCLKIN
--------------------- -
=
=
------------
2
2
M
M

N

P

P

FCLKIN
--------------------- -

FCLKIN
----------------------
M
N
N

FCLKIN
--------------------- -
N
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
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