LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 721
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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32.5.8 UART Line Status Register
Table 672. UART Line Control Register (LCR - addresses 0x4008 100C (UART0), 0x400C
The LSR is a Read Only register that provides status information on the UART TX and RX
blocks.
Table 673. UART Line Status Register Read Only (LSR - addresses 0x4008 1014 (UART0),
Bit
3
5:4
6
7
31:
8
Bit Symbol
0
1
OE
RDR
Symbol Value Description
PE
PS
BC
DLAB
-
100C (UART2), 0x400C 200C (UART3)) bit description
0x400C 1014 (UART2), 0x400C 2014 (UART3) ) bit description
0
1
0x0
0x1
0x2
0x3
0
1
0
1
-
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
Parity Enable
Disable parity generation and checking.
Enable parity generation and checking.
Parity Select.
Odd parity. Number of 1s in the transmitted character and the
attached parity bit will be odd.
Even Parity. Number of 1s in the transmitted character and the
attached parity bit will be even.
Forced "1" stick parity.
Forced "0" stick parity.
Break Control.
Disable break transmission.
Enable break transmission. Output pin UART TXD is forced to logic
0 when LCR[6] is active high.
Divisor Latch Access Bit.
Disable access to Divisor Latches.
Enable access to Divisor Latches.
Reserved
Rev. 00.13 — 20 July 2011
Receiver Data Ready.
LSR[0] is set when the RBR holds an unread character and is
cleared when the UART RBR FIFO is empty.
RBR is empty.
RBR contains valid data.
Overrun Error.
The overrun error condition is set as soon as it occurs. A LSR
read clears LSR[1]. LSR[1] is set when UART RSR has a new
character assembled and the UART RBR FIFO is full. In this
case, the UART RBR FIFO will not be overwritten and the
character in the UART RSR will be lost.
Overrun error status is inactive.
Overrun error status is active.
Chapter 32: LPC18xx USART0_2_3
…continued
UM10430
© NXP B.V. 2011. All rights reserved.
721 of 1164
Reset
Value
0
0
0
0
-
Reset
Value
0
0
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