LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 506

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 429. DMA Interrupt enable register (DMA_INT_EN, address 0x4001 101C) bit description
<Document ID>
User manual
Bit
6
7
8
9
10
12:11
13
14
Symbol
RIE
RUE
RSE
RWE
ETE
-
FBE
ERE
Description
Receive interrupt enable
When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register),
Receive Interrupt is enabled. When this bit is reset, Receive Interrupt is disabled.
Receive buffer unavailable enable
When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register),
Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive
Buffer Unavailable Interrupt is disabled.
Received stopped enable
When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register),
Receive Stopped Interrupt is enabled. When this bit is reset, Receive Stopped
Interrupt is disabled.
Receive watchdog timeout enable
When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register),
the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, Receive
Watchdog Timeout Interrupt is disabled.
Early transmit interrupt enable
When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this
register), Early Transmit Interrupt is enabled. When this bit is reset, Early Transmit
Interrupt is disabled.
Reserved
Fatal bus error enable
When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register),
the Fatal Bus Error Interrupt is enabled. When this bit is reset, Fatal Bus Error Enable
Interrupt is disabled.
Early receive interrupt enable
When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register),
Early Receive Interrupt is enabled. When this bit is reset, Early Receive Interrupt is
disabled.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
…continued
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
0
0
0
506 of 1164
Access
R/W
R/W
R/W
R/W
R/W
RO
R/W
R/W