LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 671

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
27.6.1.1 QEI Control register
27.6.1.2 QEI Configuration register
27.6.1 Control registers
This register contains bits which control the operation of the position and velocity counters
of the QEI module.
Table 575: QEI Control register (CON - address 0x400C 6000) bit description
This register contains the configuration of the QEI module.
Table 576: QEI Configuration register (CONF - address 0x400C 6008) bit description
Bit
0
1
2
3
31:4
Bit
0
1
2
3
4
15:5
19:16
31:20
Symbol
RESP
RESPI
RESV
RESI
-
Symbol
DIRINV
SIGMODE
CAPMODE Capture Mode. When = 0, only PhA edges are counted (2X).
INVINX
CRESPI
-
INXGATE
-
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Description
Reset position counter. When set = 1, resets the position counter to
all zeros. Autoclears when the position counter is cleared.
Reset position counter on index. When set = 1, resets the position
counter to all zeros when an index pulse occurs. Autoclears when
the position counter is cleared.
Reset velocity. When set = 1, resets the velocity counter to all zeros
and reloads the velocity timer. Autoclears when the velocity counter
is cleared.
Reset index counter. When set = 1, resets the index counter to all
zeros. Autoclears when the index counter is cleared.
reserved
Description
Direction invert. When = 1, complements the DIR bit.
Signal Mode. When = 0, PhA and PhB function as quadrature
encoder inputs. When = 1, PhA functions as the direction signal
and PhB functions as the clock signal.
When = 1, BOTH PhA and PhB edges are counted (4X),
increasing resolution but decreasing range.
Invert Index. When set, inverts the sense of the index input.
Continuously reset position counter on index. When set = 1,
resets the position counter to all zeros when an index pulse
occurs at the next position increase (recalibration). Auto-clears
when the position counter is cleared.
Reserved
Index gating configuration:
when INXGATE(19)=1, pass the index when Pha=0 and Phb=0,
else block.
when INXGATE(18)=1, pass the index when Pha=0 and Phb=1,
else block.
when INXGATE(17)=1, pass the index when Pha=1 and Phb=1,
else block.
when INXGATE(16)=1, pass the index when Pha=1 and Phb=0,
else block.
reserved
Rev. 00.13 — 20 July 2011
Chapter 27: LPC18xx Quadrature Encoder Interface (QEI)
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0
0
0
1111
0
Reset
value
0
0
0
0
0