LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 106
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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10.5.2 Base clock status register
Table 80.
Each bit in this register indicates if the specified base clock can be safely switched off. A
logic zero indicates that all branch clocks generated from this base clock are disabled.
Hence, the base clock can also be switched off. A logic one value indicates that there is
still at least one branch clock running.
Remark: The base clock must be reactivated before writing to the configuration register of
the branch clock.
Table 81.
Bit
0
31:1
Bit
0
1
2
3
6:4
7
8
31:9 -
Symbol
BASE_APB3_
CLK_IND
BASE_APB1_
CLK_IND
BASE_SPIFI_
CLK_IND
BASE_M3_
CLK_IND
-
BASE_USB0_
CLK_IND
BASE_USB1_
CLK_IND
Symbol
PD
-
CCU1/2 power mode register (CCU1_PM, address 0x4005 1000 and CCU2_PM,
address 0x4005 2000) bit description
CCU1 base clock status register (CCU1_BASE_STAT, address 0x4005 1004) bit
description
All information provided in this document is subject to legal disclaimers.
Value
0
1
Rev. 00.13 — 20 July 2011
Description
Initiate power-down mode
Normal operation.
Clocks with wake-up mode enabled (W = 1) are
disabled.
Reserved.
Description
Base clock indicator for BASE_APB3_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.
Base clock indicator for BASE_APB1_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.
Base clock indicator for BASE_SPIFI_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.
Base clock indicator for BASE_M3_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.
Reserved
Base clock indicator for BASE_USB0_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.
Base clock indicator for BASE_USB1_CLK
0 = All branch clocks switched off.
1 = at least one branch clock running.
Reserved
Chapter 10: LPC18xx Clock Control Unit (CCU)
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
-
Reset
value
1
1
1
1
-
1
1
-
106 of 1164
Access
R/W
-
Access
R
R
R
R
-
R
R
-
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