LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 1143

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
43.4 Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. CMAC generation . . . . . . . . . . . . . . . . . . . . . . . .28
Fig 11. UART boot process . . . . . . . . . . . . . . . . . . . . . . .29
Fig 12. SPIFI boot process . . . . . . . . . . . . . . . . . . . . . . .30
Fig 13. EMC boot process . . . . . . . . . . . . . . . . . . . . . . . .30
Fig 14. SPI boot process . . . . . . . . . . . . . . . . . . . . . . . . .31
Fig 15. Boot process timing . . . . . . . . . . . . . . . . . . . . . . .32
Fig 16. AES engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Fig 17. CGU and CCU0/1 block diagram. . . . . . . . . . . . .67
Fig 18. CGU block diagram . . . . . . . . . . . . . . . . . . . . . . .70
Fig 19. PLL0 block diagram . . . . . . . . . . . . . . . . . . . . . . .91
Fig 20. PLL1 block diagram . . . . . . . . . . . . . . . . . . . . . . .95
Fig 21. RGU Block diagram . . . . . . . . . . . . . . . . . . . . . . 111
Fig 22. RGU Reset structure . . . . . . . . . . . . . . . . . . . . . 114
Fig 23. GIMA input stages . . . . . . . . . . . . . . . . . . . . . . .223
Fig 24. Cross connections between GIMA, SCT, and
Fig 25. Cross connections between GIMA, ADC, and event
Fig 26. DMA controller block diagram . . . . . . . . . . . . . .282
Fig 27. LLI example . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
Fig 28. SD/MMC block diagram . . . . . . . . . . . . . . . . . . .297
Fig 29. EMC block diagram . . . . . . . . . . . . . . . . . . . . . .324
Fig 30. EMC block diagram . . . . . . . . . . . . . . . . . . . . . .346
Fig 31. 32 bit bank external memory interfaces ( bits
Fig 32. 16 bit bank external memory interfaces (bits
Fig 33. 8 bit bank external memory interface (bits MW = 00)
Fig 34. Typical memory configuration diagram . . . . . . .353
Fig 35. High-speed USB OTG block diagram . . . . . . . .355
Fig 36. USB controller modes . . . . . . . . . . . . . . . . . . . .360
Fig 37. Endpoint queue head organization . . . . . . . . . .406
Fig 38. Endpoint queue head data structure . . . . . . . . .408
Fig 39. Device state diagram . . . . . . . . . . . . . . . . . . . . .414
Fig 40. Endpoint queue head diagram. . . . . . . . . . . . . .426
Fig 41. Software link pointers. . . . . . . . . . . . . . . . . . . . .428
Fig 42. Device power state diagram . . . . . . . . . . . . . . .433
<Document ID>
User manual
LPC18xx Block diagram (flashless parts) . . . . . .10
LPC18xx AHB multilayer matrix connections
(flashless parts) . . . . . . . . . . . . . . . . . . . . . . . . . . 11
LPC185x/3x/2x/1x block diagram (parts with on-chip
flash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
AHB multilayer matrix master and slave connections
13
System memory map - flashless parts
LPC1850/30/20/10 (see
addresses of all peripherals) . . . . . . . . . . . . . . . .17
Memory map with peripherals - flashless parts
LPC1850/30/20/10 (see
addresses of memory blocks) . . . . . . . . . . . . . . .18
System memory map - parts with on-chip flash
(overview) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Memory mapping - parts with on-chip flash
(peripherals). . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Boot process . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
timer0/1/2/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
MW = 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
MW = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
352
Figure 6
Figure 5
for detailed
for detailed
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Fig 43. Host/OTG power state diagram . . . . . . . . . . . . 435
Fig 44. Interrupt generation. . . . . . . . . . . . . . . . . . . . . . 507
Fig 45. Wake-up frame filter register . . . . . . . . . . . . . . . 510
Fig 46. Descriptor ring and chain structure . . . . . . . . . . 515
Fig 47. TxDMA operation in default mode. . . . . . . . . . . 519
Fig 48. TxDMA operation in OSF mode . . . . . . . . . . . . 521
Fig 49. Receive DMA operation . . . . . . . . . . . . . . . . . . 524
Fig 50. Transmitter descriptor fields - enhanced format 528
Fig 51. Transmit descriptor fetch (read) for enhanced format
Fig 52. Receive descriptor fields - alternate (enhanced
Fig 53. LCD controller block diagram . . . . . . . . . . . . . . 564
Fig 54. Cursor movement . . . . . . . . . . . . . . . . . . . . . . . 572
Fig 55. Cursor clipping . . . . . . . . . . . . . . . . . . . . . . . . . 573
Fig 56. Cursor image format . . . . . . . . . . . . . . . . . . . . . 574
Fig 57. Power-up and power-down sequences. . . . . . . 580
Fig 58. Horizontal timing for STN displays . . . . . . . . . . 581
Fig 59. Vertical timing for STN displays . . . . . . . . . . . . 582
Fig 60. Horizontal timing for TFT displays. . . . . . . . . . . 582
Fig 61. Vertical timing for TFT displays . . . . . . . . . . . . . 583
Fig 62. SCT block diagram . . . . . . . . . . . . . . . . . . . . . . 588
Fig 63. SCT counter and select logic . . . . . . . . . . . . . . 589
Fig 64. Match logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
Fig 65. Capture logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
Fig 66. Event selection . . . . . . . . . . . . . . . . . . . . . . . . . 612
Fig 67. Output slice i . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
Fig 68. SCT interrupt generation. . . . . . . . . . . . . . . . . . 612
Fig 69. SCT configuration example. . . . . . . . . . . . . . . . 619
Fig 70. A timer cycle in which PR=2, MRx=6, and both
Fig 71. A timer Cycle in Which PR=2, MRx=6, and both
Fig 72. Timer block diagram . . . . . . . . . . . . . . . . . . . . . 634
Fig 73. MCPWM Block Diagram . . . . . . . . . . . . . . . . . . 637
Fig 74. Edge-aligned PWM waveform without dead time,
Fig 75. Center-aligned PWM waveform without dead time,
Fig 76. Edge-aligned PWM waveform with dead time,
Fig 77. Center-aligned waveform with dead time, POLA = 0
Fig 78. Three-phase DC mode sample waveforms. . . . 664
Fig 79. Three-phase AC mode sample waveforms, edge
Fig 80. Encoder interface block diagram. . . . . . . . . . . . 668
Fig 81. Quadrature Encoder Basic Operation . . . . . . . . 682
Fig 82. RI timer block diagram . . . . . . . . . . . . . . . . . . . 687
Fig 83. Watchdog block diagram. . . . . . . . . . . . . . . . . . 697
Fig 84. Early Watchdog Feed with Windowed Mode
Fig 85. Correct Watchdog Feed with Windowed Mode
Fig 86. Watchdog Warning Interrupt . . . . . . . . . . . . . . . 698
Fig 87. RTC functional block diagram . . . . . . . . . . . . . . 700
529
format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
interrupt and reset on match are enabled. . . . . 633
interrupt and stop on match are enabled . . . . . 633
POLA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
POLA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
POLA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
662
aligned PWM mode. . . . . . . . . . . . . . . . . . . . . . 665
Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698
Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698
Chapter 43: Supplementary information
UM10430
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