LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 296
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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18.1 How to read this chapter
18.2 Basic configuration
18.3 Features
18.4 General description
<Document ID>
User manual
The SD/MMC card interface is available on LPC18xx Rev ‘A’.
Table 222. SDIO clocking and power control
The SDIO is reset by the SD_RST (reset # 20).
The SD/MMC card interface supports the following modes:
<tbd>
SDIO register
interface
SDIO bit rate clock
•
•
•
•
UM10430
Chapter 18: LPC18xx SD/MMC interface
Rev. 00.13 — 20 July 2011
Secure Digital memory (SD version 3.0)
Secure Digital I/O (SDIO version 2.0)
Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1)
Multimedia Cards (MMC version 4.4)
All information provided in this document is subject to legal disclaimers.
Base clock
BASE_M3_CLK
BASE_SDIO_CLK
Rev. 00.13 — 20 July 2011
Branch clock
CLK_M3_SDIO
CLK_SDIO
© NXP B.V. 2011. All rights reserved.
Maximum
frequency
150 MHz
<tbd>
User manual
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