LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 1147

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
6.6.8
Chapter 7: LPC18xx Configuration Registers (CREG)
7.1
7.2
7.3
7.4
7.4.1
7.4.2
7.4.3
Chapter 8: LPC18xx Power Management Controller (PMC)
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.3
Chapter 9: LPC18xx Clock Generation Unit (CGU)
9.1
9.2
9.3
9.4
9.5
9.6
9.6.1
9.6.2
9.6.3
9.6.3.1
9.6.3.2
9.6.3.3
9.6.3.4
9.6.4
9.6.4.1
9.6.4.2
9.6.4.3
9.6.4.4
9.6.4.5
9.6.5
9.6.5.1
9.6.5.2
9.6.6
9.6.7
9.6.8
9.6.9
9.6.10
9.6.11
9.6.12
9.6.13
9.6.14
9.6.15
<Document ID>
User manual
How to read this chapter . . . . . . . . . . . . . . . . . 54
Basic configuration . . . . . . . . . . . . . . . . . . . . . 54
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Register description . . . . . . . . . . . . . . . . . . . . 55
How to read this chapter . . . . . . . . . . . . . . . . . 62
General description . . . . . . . . . . . . . . . . . . . . . 62
Register description . . . . . . . . . . . . . . . . . . . . 64
How to read this chapter . . . . . . . . . . . . . . . . . 66
Basic configuration . . . . . . . . . . . . . . . . . . . . . 66
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
General description . . . . . . . . . . . . . . . . . . . . . 66
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 71
Register description . . . . . . . . . . . . . . . . . . . . 71
Set status register. . . . . . . . . . . . . . . . . . . . . . 52
IRC trim register . . . . . . . . . . . . . . . . . . . . . . . 55
CREG0 control register . . . . . . . . . . . . . . . . . 56
Power mode control register. . . . . . . . . . . . . . 56
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 63
Power-down mode . . . . . . . . . . . . . . . . . . . . . 63
Deep power-down . . . . . . . . . . . . . . . . . . . . . 63
Frequency monitor register . . . . . . . . . . . . . . 73
Crystal oscillator control register . . . . . . . . . . 74
PLL0 (for USB) registers . . . . . . . . . . . . . . . . 75
PLL0 (for USB) status register . . . . . . . . . . . . 75
PLL0 (for USB) control register. . . . . . . . . . . . 75
PLL0 (for USB) M-divider register. . . . . . . . . . 76
PLL0 (for USB) NP-divider register. . . . . . . . . 77
PLL0 (for audio) registers . . . . . . . . . . . . . . . . 77
PLL0 (for audio) status register . . . . . . . . . . . 77
PLL0 (for audio) control register . . . . . . . . . . . 77
PLL0 (for audio) M-divider register . . . . . . . . . 79
PLL0 (for audio) NP-divider register . . . . . . . . 79
PLL0 (for audio) fractional divider register . . . 79
PLL1 registers . . . . . . . . . . . . . . . . . . . . . . . . 79
PLL1 status register . . . . . . . . . . . . . . . . . . . . 79
PLL1 control register . . . . . . . . . . . . . . . . . . . 80
Integer divider register A . . . . . . . . . . . . . . . . 81
Integer divider register B, C, D . . . . . . . . . . . . 82
Integer divider register E . . . . . . . . . . . . . . . . 83
Output stage 0 control register . . . . . . . . . . . . 84
Output stage 1 control register . . . . . . . . . . . . 84
Output stage 3 control register . . . . . . . . . . . . 85
Output stage 4 to 19 control registers. . . . . . . 86
Output stage 20 register . . . . . . . . . . . . . . . . . 87
Output stage 25 register . . . . . . . . . . . . . . . . . 88
Output stage 26 to 27 register . . . . . . . . . . . . 89
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
8.3.1
8.3.2
8.4
8.4.1
8.4.2
9.7
9.7.1
9.7.2
9.7.3
9.7.4
9.7.4.1
9.7.4.2
9.7.4.3
9.7.4.3.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . 92
9.7.4.3.2 Mode 1a: Normal operating mode without
9.7.4.3.3 Mode 1b: Normal operating mode with
9.7.4.3.4 Mode 1c: Normal operating mode without
9.7.4.3.5 Mode 1d: Normal operating mode with
9.7.4.3.6 Mode 3: Power down mode (pd) . . . . . . . . . . 93
9.7.4.4
9.7.4.5
9.7.5
9.7.6
9.7.6.1
9.7.6.2
9.7.6.3
9.7.6.4
9.7.6.5
9.7.6.6
9.7.6.7
Functional description . . . . . . . . . . . . . . . . . . 65
Functional description . . . . . . . . . . . . . . . . . . 90
ARM Cortex-M3 memory mapping register . . 57
CREG5 control register . . . . . . . . . . . . . . . . . 57
DMA muxing register . . . . . . . . . . . . . . . . . . . 57
ETB SRAM configuration register . . . . . . . . . 60
CREG6 control register . . . . . . . . . . . . . . . . . 60
Part ID register. . . . . . . . . . . . . . . . . . . . . . . . 61
Hardware sleep event enable register
PD0_SLEEP0_HW_ENA . . . . . . . . . . . . . . . . 64
Sleep power mode register PD0_SLEEP0_MODE
64
Run-time programming . . . . . . . . . . . . . . . . . 65
Power API . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
32 kHz oscillator. . . . . . . . . . . . . . . . . . . . . . . 90
IRC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 90
PLL0 (for USB and audio) . . . . . . . . . . . . . . . 90
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
PLL0 description . . . . . . . . . . . . . . . . . . . . . . 91
Use of PLL0 operating modes . . . . . . . . . . . . 92
post-divider and without pre-divider . . . . . . . . 92
post-divider and without pre-divider . . . . . . . . 93
post-divider and with pre-divider . . . . . . . . . . 93
post-divider and with pre-divider . . . . . . . . . . 93
Settings for USB0 . . . . . . . . . . . . . . . . . . . . . 93
Usage notes. . . . . . . . . . . . . . . . . . . . . . . . . . 94
Fractional divider for the PLL0 (for audio) . . . 94
PLL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
PLL1 description . . . . . . . . . . . . . . . . . . . . . . 95
Lock detector . . . . . . . . . . . . . . . . . . . . . . . . . 95
Power-down control . . . . . . . . . . . . . . . . . . . . 95
Selectable feedback divider clock . . . . . . . . . 96
Direct output mode. . . . . . . . . . . . . . . . . . . . . 96
Divider ratio programming . . . . . . . . . . . . . . . 96
Pre-divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Post-divider . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Feedback divider . . . . . . . . . . . . . . . . . . . . . . . 96
Changing the divider values. . . . . . . . . . . . . . . 96
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
1147 of 1164