LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 583
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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23.9 LCD panel signal usage
Table 494. LCD panel connections for STN single panel mode
<Document ID>
User manual
External pin
LCDVD23
LCDVD22
LCDVD21
LCDVD20
LCDVD19
LCDVD18
LCDVD17
LCDVD16
LCDVD15
LCDVD14
LCDVD13
LCDVD12
LCDVD11
LCDVD10
LCDVD9
Fig 61. Vertical timing for TFT displays
(vertical synch
(data enable)
control signals
(panel clock)
and horizontal
for one frame
(1) Polarities may vary for some displays.
LCDDCLK
LCDENA
pixel data
LCDFP
pulse)
4-bit mono STN single panel
LPC18xx pin
used
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LCD_TIMV (VSW)
LCD function
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(defined in line clocks)
All information provided in this document is subject to legal disclaimers.
panel data clock active
LCD_TIMV (VBP)
back porch
Rev. 00.13 — 20 July 2011
8-bit mono STN single panel
LPC18xx pin
used
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data enable
one frame
see horizontal timing for TFT displays
all horizontal lines for one frame
LCD function
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LCD_TIMV(LPP)
Color STN single panel
LPC18xx pin
used
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Chapter 23: LPC18xx LCD
(defined in line clocks)
LCD_TIMV (VFP)
UM10430
front porch
© NXP B.V. 2011. All rights reserved.
LCD function
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583 of 1164
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