LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 287

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
16.8.1.6 Halting a DMA channel
16.8.1.7 Programming a DMA channel
16.8.2 Flow control
Set the halt bit in the relevant DMA channel configuration register. The current source
request is serviced. Any further source DMA request is ignored until the halt bit is cleared.
The peripheral that controls the length of the packet is known as the flow controller. The
flow controller is usually the DMA Controller where the packet length is programmed by
software before the DMA channel is enabled. If the packet length is unknown when the
DMA channel is enabled, either the source or destination peripherals can be used as the
flow controller.
For simple or low-performance peripherals that know the packet length (that is, when the
peripheral is the flow controller), a simple way to indicate that a transaction has completed
is for the peripheral to generate an interrupt and enable the processor to reprogram the
DMA channel.
The transfer size value (in the CCONTROL register) is ignored if a peripheral is configured
as the flow controller.
When the DMA transfer is completed:
The following sections describe the DMA Controller data flow sequences for the four
allowed transfer types:
3. Program the DMA controller
1. Choose a free DMA channel with the priority needed. DMA channel 0 has the highest
2. Clear any pending interrupts on the channel to be used by writing to the IntTCClear
3. Write the source address into the CSRCADDR register.
4. Write the destination address into the CDESTADDR register.
5. Write the address of the next LLI into the CLLI register. If the transfer comprises of a
6. Write the control information into the CCONTROL register.
7. Write the channel configuration information into the CCONFIG register. If the enable
1. The DMA Controller issues an acknowledge to the peripheral in order to indicate that
2. A TC interrupt is generated, if enabled.
3. The DMA Controller moves on to the next LLI.
•
•
•
priority and DMA channel 7 the lowest priority.
and INTERRCLEAR register. The previous channel operation might have left interrupt
active.
single packet of data then 0 must be written into this register.
bit is set then the DMA channel is automatically enabled.
the transfer has finished.
Memory-to-peripheral (master 1 only).
Peripheral-to-memory (master 1 only).
Memory-to-memory.
All information provided in this document is subject to legal disclaimers.
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
UM10430
© NXP B.V. 2011. All rights reserved.
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