LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 849

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LPC1810FET100,551

Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr

Specifications of LPC1810FET100,551

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
NXP Semiconductors
<Document ID>
User manual
36.7.4 Interrupt handling
If several interrupts are pending, the CAN Interrupt Register will point to the pending
interrupt with the highest priority, disregarding their chronological order. An interrupt
remains pending until the CPU has cleared it.
Fig 129. Reading a message from the FIFO buffer to the message buffer
INTID = 0x8000 ?
interrupt handling
status change
All information provided in this document is subject to legal disclaimers.
yes
Rev. 00.13 — 20 July 2011
write MessageNum to CANIFx_CMDREQ
MessageNum = MessageNum +1
read message to message buffer
read data from CANIFx_DA/B
MessageNum = INTID
read CANIFx_MCTRL
reset NEWDAT = 0
reset INTPND = 0
INTID = 0x0001
NEWDAT = 1
read CANIR
to 0x0020 ?
EOB = 1
START
no
yes
yes
no
yes
Chapter 36: LPC18xx C_CAN
INTID = 0x0000 ?
END
UM10430
yes
© NXP B.V. 2011. All rights reserved.
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