LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 210

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
13.4.6 Pin configuration register for USB1 pins DP1/DM1
13.4.7 Pin configuration register for open-drain I
Table 118. Analog function select register (ENAIO2, address 0x4008 6C90) bit description
Remark: The USB_ESEA bit must be set to one to use USB1.
Table 119. Pin configuration for pins DP1/DM1 register (SFSUSB, address 0x4008 6C80) bit
Table 120. Pin configuration for open-drain I
Bit
0
3:1
4
31:5
Bit
0
1
31:2 -
Bit
0
1. Tri-state the output driver by selecting an input at the pinmux e.g. GPIO function in
2. Disable the receiver by setting the EZI bit to zero (see
3. Disable the pull-up resistor by setting the EPUN bit to one, and disable the pull-down
input mode.
the default setting.
resistor by setting the EPD bit to zero.
Symbol
DAC
BG
Symbol
USB_AIM
USB_ESEA
Symbol
SDA_EHS
description
6C84) bit description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
Value Description
0
1
0
1
Rev. 00.13 — 20 July 2011
Value
0
1
Select DAC
Analog function DAC selected on pin P4_4.
Digital function selected on pin P4_4.
Reserved
Select band gap output
Band gap output selected for pin PF_7.
Digital function selected on pin PF_7.
Reserved
Differential data input AIP/AIM
0 = Going LOW with full speed edge rate
1 = Going HIGH with full speed edge rate
Going LOW with full speed edge rate
Going HIGH with full speed edge rate
Control signal for differential input or single input
Reserved. Do not use.
Single input AIP. Enables USB1.
Reserved
Description
Configures I
Standard/Fast mode (400 kbit/s)
High-speed mode (3.4 Mbit/s)
Chapter 13: LPC18xx System Control Unit (SCU)
2
2
C0-bus speed for SDA0 pin
C-bus pins register (SFSI2C0, address 0x4008
2
C-bus pins
Table 111
or
UM10430
Table
© NXP B.V. 2011. All rights reserved.
Reset
value
0
Reset
value
0
-
0
-
Reset
value
0
0
-
112). This is
210 of 1164
Access
R/W
-
R/W
-
Access
R/W
R/W
-
Access
R/W