LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 777

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
34.6.10 SSP DMA Control Register
34.6.9 SSP Interrupt Clear Register
Table 723: SSP Masked Interrupt Status register (MIS -address 0x4008 301C (SSP0),
Software can write one or more one(s) to this write-only register, to clear the
corresponding interrupt condition(s) in the SSP controller. Note that the other two interrupt
conditions can be cleared by writing or reading the appropriate FIFO, or disabled by
clearing the corresponding bit in SSPnIMSC.
Table 724: SSP interrupt Clear Register (ICR - address 0x4008 3020 (SSP0), ICR -
The SSPnDMACR register is the DMA control register. It is a read/write register.
Bit
0
1
2
3
31:4
Bit
0
1
31:2
Symbol
RORIC
RTIC
-
Symbol
RORMIS
RTMIS
RXMIS
TXMIS
-
0x400C 501C (SSP1)) bit description
0x400C 5020 (SSP1)) bit description
All information provided in this document is subject to legal disclaimers.
Description
Writing a 1 to this bit clears the “frame was received when RxFIFO was
full” interrupt.
Writing a 1 to this bit clears the Rx FIFO was not empty and has not
been read for a time-out period interrupt. The time-out period is the same
for master and slave modes and is determined by the SSP bit rate: 32
bits at PCLK / (CPSDVSR  [SCR+1]).
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
This bit is 1 if another frame was completely received while the RxFIFO
This bit is 1 if the Rx FIFO is at least half full, and this interrupt is
Description
was full, and this interrupt is enabled.
This bit is 1 if the Rx FIFO is not empty, has not been read for a
time-out period, and this interrupt is enabled. The time-out period is the
same for master and slave modes and is determined by the SSP bit
rate: 32 bits at PCLK / (CPSDVSR  [SCR+1]).
enabled.
This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is
enabled.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 00.13 — 20 July 2011
Chapter 34: LPC18xx SSP0/1
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0
NA
Reset
value
NA
NA
NA