LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 314
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Table 244. FIFO Threshold Watermark Register (FIFOTH, address 0x4000 404C) bit description
<Document ID>
User manual
Bit
30:28
31
Symbol
DW_DMA_MUTIP
LE_
TRANSACTION_
SIZE
-
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
All information provided in this document is subject to legal disclaimers.
Description
Burst size of multiple transaction; should be programmed same as
DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The
units for transfers is the H_DATA_WIDTH parameter. A single transfer
(dw_dma_single assertion in case of Non DW DMA interface) would
be signalled based on this value. Value should be sub-multiple of
(RX_WMark + 1)* (F_DATA_WIDTH/H_DATA_WIDTH) and
(FIFO_DEPTH - TX_WMark)* (F_DATA_WIDTH/ H_DATA_WIDTH)
For example, if FIFO_DEPTH = 16, FDATA_WIDTH ==
H_DATA_WIDTH
Allowed combinations for MSize and TX_WMark are:
MSize = 1,
TX_WMARK = 1-15
MSize = 4,
TX_WMark = 8
MSize = 4,
TX_WMark = 4
MSize = 4,
TX_WMark = 12
MSize = 8,
TX_WMark = 8
MSize = 8,
TX_WMark = 4.
Allowed combinations for MSize and RX_WMark are:
MSize = 1,
RX_WMARK = 0-14
MSize = 4,
RX_WMark = 3
MSize = 4,
RX_WMark = 7
MSize = 4,
RX_WMark = 11
MSize = 8,
RX_WMark = 7
MSize = 8,
RX_WMark = 11
Recommended: MSize = 8, TX_WMark = 8, RX_WMark = 7
1 transfer
4 transfers
8 transfers
16 transfers
32 transfers
64 transfers
128 transfers
256 transfers
Reserved
Rev. 00.13 — 20 July 2011
Chapter 18: LPC18xx SD/MMC interface
UM10430
© NXP B.V. 2011. All rights reserved.
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