LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 656
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Table 568. MCPWM Count Control read address (CNTCON - 0x400A 005C) bit description
<Document ID>
User manual
Bit
10
11
12
13
14
15
16
17
28:18 -
29
30
31
Symbol
TC1MCI2_RE
TC1MCI2_FE
TC2MCI0_RE
TC2MCI0_FE
TC2MCI1_RE
TC2MCI1_FE
TC2MCI2_RE
TC2MCI2_FE
CNTR0
CNTR1
CNTR2
26.7.10.2 MCPWM Count Control set address
Writing one(s) to this write-only address sets the corresponding bit(s) in CNTCON.
Value Description
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-
0
1
0
1
0
1
Counter 1 rising edge mode, channel 2.
A rising edge on MCI2 does not affect counter 1.
If MODE1 is 1, counter 1 advances on a rising edge on MCI2.
Counter 1 falling edge mode, channel 2.
A falling edge on MCI2 does not affect counter 1.
If MODE1 is 1, counter 1 advances on a falling edge on MCI2.
Counter 2 rising edge mode, channel 0.
A rising edge on MCI0 does not affect counter 2.
If MODE2 is 1, counter 2 advances on a rising edge on MCI0.
Counter 2 falling edge mode, channel 0.
A falling edge on MCI0 does not affect counter 2.
If MODE2 is 1, counter 2 advances on a falling edge on MCI0.
Counter 2 rising edge mode, channel 1.
A rising edge on MCI1 does not affect counter 2.
If MODE2 is 1, counter 2 advances on a rising edge on MCI1.
Counter 2 falling edge mode, channel 1.
A falling edge on MCI1 does not affect counter 2.
If MODE2 is 1, counter 2 advances on a falling edge on MCI1.
Counter 2 rising edge mode, channel 2.
A rising edge on MCI2 does not affect counter 2.
If MODE2 is 1, counter 2 advances on a rising edge on MCI2.
Counter 2 falling edge mode, channel 2.
A falling edge on MCI2 does not affect counter 2.
If MODE2 is 1, counter 2 advances on a falling edge on MCI2.
Reserved.
Channel 0 counter/timer mode.
Channel 0 is in timer mode.
Channel 0 is in counter mode.
Channel 1 counter/timer mode.
Channel 1 is in timer mode.
Channel 1 is in counter mode.
Channel 2 counter/timer mode.
Channel 2 is in timer mode.
Channel 2 is in counter mode.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
UM10430
© NXP B.V. 2011. All rights reserved.
656 of 1164
Reset
value
0
0
0
0
0
0
0
0
-
0
0
0
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