LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 625

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
25.7.2 Timer control registers
25.7.3 Timer counter registers
25.7.4 Timer prescale registers
Table 534. Timer interrupt registers IR(IR - addresses 0x4008 4000 (TIMER0), 0x4008 5000
The Timer Control Register (TCR) is used to control the operation of the Timer/Counter.
Table 535. Timer control register TCR (TCR - addresses 0x4008 4004 (TIMER0), 0x4008 5004
The 32-bit Timer Counter register is incremented when the prescale counter reaches its
terminal count. Unless it is reset before reaching its upper limit, the Timer Counter will
count up through the value 0xFFFF FFFF and then wrap back to the value 0x0000 0000.
This event does not cause an interrupt, but a match register can be used to detect an
overflow if needed.
Table 536. Timer counter registers TC (TC - addresses 0x4008 4008 (TIMER0), 0x4008 5008
The 32-bit Timer prescale register specifies the maximum value for the Prescale Counter.
Table 537. Timer prescale registers PR (PR - addresses 0x4008 400C (TIMER0), 0x4008 500C
Bit
6
7
31:8
Bit
0
1
31:2
Bit
31:0
Bit
31:0
Symbol
CEN
CRST
-
Symbol
CR2INT
CR3INT
-
Symbol
TC
Symbol
PM
(TIMER1), 0x400C 3000 (TIMER3), 0x400C 4000 (TIMER4)) bit description
(TIMER1), 0x400C 3003 (TIMER2), 0x400C 4004 (TIMER3)) bit description
(TIMER1), 0x400C 3008 (TIMER2), 0x400C 4008 (TIMER3)) bit description
(TIMER1), 0x400C 300C (TIMER2), 0x400C 400C (TIMER3)) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Interrupt flag for capture channel 2 event.
Interrupt flag for capture channel 3 event.
Reserved.
Description
Timer counter value.
Description
Prescale counter maximum value.
Description
When one, the Timer Counter and Prescale Counter are
enabled for counting. When zero, the counters are
disabled.
When one, the Timer Counter and the Prescale Counter
are synchronously reset on the next positive edge of
PCLK. The counters remain reset until TCR[1] is
returned to zero.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Chapter 25: LPC18xx Timer0/1/2/3
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0
0
NA
625 of 1164
Reset
value
0
0
-
Reset
value
0
Reset
value
0