LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 406
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Fig 37. Endpoint queue head organization
ENDPOINTLISTADDR
20.9.1.1 Endpoint capabilities and characteristics
20.9.1 Endpoint queue head (dQH)
Device queue heads are arranged in an array in a continuous area of memory pointed to
by the ENDPOINTLISTADDR pointer. The even –numbered device queue heads in the list
support receive endpoints (OUT/SETUP) and the odd-numbered queue heads in the list
are used for transmit endpoints (IN/INTERRUPT). The device controller will index into this
array based upon the endpoint number received from the USB bus. All information
necessary to respond to transactions for all primed transfers is contained in this list so the
Device Controller can readily respond to incoming requests without having to traverse a
linked list.
Remark: The Endpoint Queue Head List must be aligned to a 2k boundary.
The device Endpoint Queue Head (dQH) is where all transfers are managed. The dQH is
a 48-byte data structure, but must be aligned on 64-byte boundaries. During priming of an
endpoint, the dTD (device transfer descriptor) is copied into the overlay area of the dQH,
which starts at the nextTD pointer DWord and continues through the end of the buffer
pointers DWords. After a transfer is complete, the dTD status DWord is updated in the
dTD pointed to by the currentTD pointer. While a packet is in progress, the overlay area of
the dQH is used as a staging area for the dTD so that the Device Controller can access
needed information with little minimal latency.
This DWord specifies static information about the endpoint, in other words, this
information does not change over the lifetime of the endpoint. Device Controller software
should not attempt to modify this information while the corresponding endpoint is enabled.
Endpoint Queue Heads
Endpoint dQH0 - Out
Endpoint dQH5 - Out
Endpoint dQH1 - Out
Endpoint dQH5 - In
Endpoint dQH0 - In
All information provided in this document is subject to legal disclaimers.
dQH
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Endpoint Transfer
Descriptors dTD
transfer buffer
dTD
dTD
dTD
pointer
transfer buffer
pointer
transfer buffer
TRANSFER
pointer
BUFFER
dTD
TRANSFER
BUFFER
TRANSFER
BUFFER
transfer buffer
pointer
TRANSFER
UM10430
BUFFER
© NXP B.V. 2011. All rights reserved.
406 of 1164
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