LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 1140

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 924. Part ID register (CHIPID, address 0x4004 3200)
Table 925. CGU clocking and power control . . . . . . . . . .978
Table 926. CGU0 base clocks . . . . . . . . . . . . . . . . . . . .979
Table 927. Clock sources for clock generators with
Table 928. Clock sources for output stages. . . . . . . . . . .980
Table 929. CGU pin description. . . . . . . . . . . . . . . . . . . .982
Table 930. Register overview: CGU (base address 0x4005
Table 931. FREQ_MON register (FREQ_MON, address
Table 932. XTAL_OSC_CTRL register (XTAL_OSC_CTRL,
Table 933. PLL0_STAT register (PLL0_STAT, address
Table 934. PLL0_CTRL register (PLL0_CTRL, address
Table 935. PLL0_MDIV register (PLL0_MDIV, address
Table 936. PLL0_NPDIV register (PLL0_NP_DIV, address
Table 937. PLL1_STAT register (PLL1_STAT, address
Table 938. PLL1_CTRL register (PLL1_CTRL, address
Table 939. IDIVA control register (IDIVA_CTRL, address
Table 940. IDIVB/C/D control registers (IDIVB_CTRL,
Table 941. IDIVE control register (IDIVE_CTRL, address
Table 942. Output stage 0 control register
Table 943. Output stage 1 control register
Table 944. Output stage 3 to 19 control registers
Table 945. Output stage 20 control register
Table 946. Recommended values for C
Table 947. Recommended values for C
<Document ID>
User manual
bit description . . . . . . . . . . . . . . . . . . . . . . . .977
selectable inputs . . . . . . . . . . . . . . . . . . . . . . .980
0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .982
0x4005 0014) bit description
address 0x4005 0018) bit description. . . . . . .985
0x4005 001C) bit description . . . . . . . . . . . . .986
0x4005 0020) bit description
0x4005 0024) bit description
0x4005 0028) bit description
0x4005 002C) bit description . . . . . . . . . . . . .988
0x4005 0030) bit description
0x4005 0034) bit description
address 0x4005 0038; IDIVC_CTRL, address
0x4005 003C; IDIVC_CTRL, address 0x4005
0040) bit description . . . . . . . . . . . . . . . . . . .990
0x4005 0044) bit description
(OUTCLK_0_CTRL, address 0x4005 0048) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .992
(OUTCLK_1_CTRL, address 0x4005 004C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .993
(OUTCLK_2_CTRL to OUTCLK_19_CTRL,
address 0x4005 0050 to 0x4005 0094) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .993
(OUTCLK_20_CTRL, addresses 0x4005 0098) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .994
mode (crystal and external components
parameters) low frequency mode . . . . . . . . .996
mode (crystal and external components
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .984
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .986
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .987
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .987
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .988
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .989
X1/X2
X1/X2
. . . . . . . . . . . .991
All information provided in this document is subject to legal disclaimers.
in oscillation
in oscillation
Rev. 00.13 — 20 July 2011
Table 948. PLL operating modes . . . . . . . . . . . . . . . . . . 998
Table 949. DIRECTL and DIRECTO bit settings in
Table 950. System PLL divider ratio settings for 12 MHz . . .
Table 951. CCU clocking and power control. . . . . . . . . 1005
Table 952. CCU1 branch clocks . . . . . . . . . . . . . . . . . . 1005
Table 953. CCU2 branch clocks . . . . . . . . . . . . . . . . . . 1007
Table 954. Register overview: CCU1 (base address 0x4005
Table 955. Register overview: CCU2 (base address 0x4005
Table 956. CCU1/2 power mode register (CCU1_PM,
Table 957. CCU1 base clock status register
Table 958. CCU2 base clock status register
Table 959. CCU1 branch clock configuration register
Table 960. CCU2 branch clock configuration register
Table 961. CCU1 branch clock status register
Table 962. CCU2 branch clock status register
Table 963. Pin description . . . . . . . . . . . . . . . . . . . . . . 1015
Table 964. SCU clocking and power control . . . . . . . . . 1040
Table 965. Register overview: System Control Unit (SCU)
Table 966. Pin configuration for pins P0_n to PF_n and CLK0
Table 967. Pin configuration for pins DP1/DM1 register
Table 968. Pin configuration for open-drain I
Table 969. EMC clock delay register (EMCCLKDELAY,
Table 970. EMC control delay register (EMCCTRLDELAY,
Table 971. EMC chip select delay register (EMCCSDELAY,
parameters) high frequency mode . . . . . . . . 997
HP0/1_Mode register . . . . . . . . . . . . . . . . . . . 999
1000
1000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008
2000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010
address 0x4005 1000 and CCU2_PM, address
0x4005 2000) bit description . . . . . . . . . . . . 1011
(CCU1_BASE_STAT, address 0x4005 1004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
(CCU2_BASE_STAT, address 0x4005 2004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
(CLK_XXX_CFG, addresses 0x4005 1100,
0x4005 1104,..., 0x4005 1A00) bit description . .
1014
(CLK_XXX_CFG, addresses 0x4005 2100,
0x4005 2200,..., 0x4005 2800) bit description . .
1014
(CLK_XXX_STAT, addresses 0x4005 1104,
0x4005 110C,..., 0x4005 1A04) bit description . .
1015
(CLK_XXX_STAT, addresses 0x4005 2104,
0x4005 2204,..., 0x4005 2804) bit description . .
1015
(base address 0x4008 6000)
to CLK3 registers (SFSPY_X, address 0x4008
6000 to 0x4008 6C0C) bit description . . . . 1047
(SFSUSB, address 0x4008 6C80) bit description
1047
register (SFSI2C0, address 0x4008 6C84) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . 1048
address 0x4008 6D00) bit description . . . . 1048
address 0x4008 6D04) bit description . . . . 1049
address 0x4008 6D08) bit description . . . . 1050
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
2
C-bus pins
1140 of 1164