LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 435
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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User manual
20.11.3 Host power states
From an operational state when a host gets a low power request, it must set the suspend
bit in the port controller. This will put an idle on the bus, block all traffic through the port,
and turn off the transceiver clock. There are two ways for a host controller to get out of the
suspend state. If it has enabled remote wake-up, a K-state on the bus will turn the
transceiver clock and generate an interrupt. The software will then have to wait 20 ms for
the resume to complete and the port to go back to an active state. Alternatively an
external event could clear the suspend bit and start the transceiver clock running again.
The software can then initiate a resume by setting the resume bit in the port controller, or
force a reconnect by setting the reset bit in the port controller.
If all devices have disconnected from the host, the host can go into a low power mode by
the software setting the suspend bit. From the disconnect-suspend state a connect event
would start the transceiver clock and interrupt the software. The software would then need
to set the reset bit to start the connect process.
Fig 43. Host/OTG power state diagram
wait for
K-state
on bus
3 ms
Low-power
All information provided in this document is subject to legal disclaimers.
request
Suspend
Resume
Suspend
signal
Wait
user-defined
Rev. 00.13 — 20 July 2011
wakeup
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Resume or
operational
Reset
Suspend bit
SW sets
(clock may be suspended)
Lock power states
disconnect
disconnect
Suspend
disconnected
all devices
interrupt
connect
user-defined
wakeup
UM10430
© NXP B.V. 2011. All rights reserved.
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