LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 551
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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23.6.5 Upper Panel Frame Base Address register
23.6.6 Lower Panel Frame Base Address register
Table 459. Line End Control register (LE, address 0x4000 800C) bit description
The UPBASE register is the color LCD upper panel DMA base address register, and is
used to program the base address of the frame buffer for the upper panel. LCDUPBase
(and LCDLPBase for dual panels) must be initialized before enabling the LCD controller.
The base address must be doubleword aligned.
Optionally, the value may be changed mid-frame to create double-buffered video displays.
These registers are copied to the corresponding current registers at each LCD vertical
synchronization. This event causes the LNBU bit and an optional interrupt to be
generated. The interrupt can be used to reprogram the base address when generating
double-buffered video.
Table 460. Upper Panel Frame Base register (UPBASE, address 0x4000 8010) bit
The LPBASE register is the color LCD lower panel DMA base address register, and is
used to program the base address of the frame buffer for the lower panel. LCDLPBase
must be initialized before enabling the LCD controller. The base address must be
doubleword aligned.
Optionally, the value may be changed mid-frame to create double-buffered video displays.
These registers are copied to the corresponding current registers at each LCD vertical
synchronization. This event causes the LNBU bit and an optional interrupt to be
generated. The interrupt can be used to reprogram the base address when generating
double-buffered video.
Bits
6:0
15:7
16
31:17
Bits
2:0
31:3
Symbol
LED
-
LEE
-
Symbol
-
LCDUPBASE
description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Line-end delay.
Controls Line-end signal delay from the rising-edge of the last
panel clock, LCDDCLK. Program with number of LCDCLK clock
periods minus 1.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
LCD Line end enable.
0 = LCDLE disabled (held LOW).
1 = LCDLE signal active.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
LCD upper panel base address.
This is the start address of the upper panel frame data in
memory and is doubleword aligned.
Chapter 23: LPC18xx LCD
UM10430
© NXP B.V. 2011. All rights reserved.
551 of 1164
Reset
value
0x0
-
0x0
-
Reset
value
-
0x0
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