LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 302
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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18.6.3 Clock Divider Register (CLKDIV)
18.6.4 SD Clock Source Register (CLKSRC)
Table 227. Clock Divider Register (CLKDIV, address 0x4000 4008) bit description
Table 228. SD Clock Source Register (CLKSRC, address 0x4000 400C) bit description
Bit
7:0
15:8
23:16
31:24
Bit
31:0
Symbol
CLK_SOURCE Clock divider source for up to 16 SD cards supported. Each card
Symbol
CLK_DIVIDER0
CLK_DIVIDER1
CLK_DIVIDER2
CLK_DIVIDER3
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
has two bits assigned to it. For example, bits[1:0] assigned for
card-0, which maps and internally routes clock divider[3:0]
outputs to cclk_out[15:0] pins, depending on bit value.
00 - Clock divider 0
01 - Clock divider 1
10 - Clock divider 2
11 - Clock divider 3
In MMC-Ver3.3-only controller, only one clock divider supported.
The cclk_out is always from clock divider 0, and this register is
not implemented.
Description
Clock divider-0 value. Clock division is 2*n. For example,
value of 0 means divide by 2*0 = 0 (no division, bypass),
value of 1 means divide by 2*1 = 2, value of ff means
divide by 2*255 = 510, and so on.
Clock divider-1 value. Clock division is 2*n. For example,
value of 0 means divide by 2*0 = 0 (no division, bypass),
value of 1 means divide by 2*1 = 2, value of ff means
divide by 2*255 = 510, and so on. In MMC-Ver3.3-only
mode, bits not implemented because only one clock divider
is supported.
Clock divider-2 value. Clock division is 2*n. For example,
value of 0 means divide by 2*0 = 0 (no division, bypass),
value of 1 means divide by 2*1 = 2, value of ff means
divide by 2*255 = 510, and so on. In MMC-Ver3.3-only
mode, bits not implemented because only one clock divider
is supported.
Clock divider-3 value. Clock division is 2*n. For example,
value of 0 means divide by 2*0 = 0 (no division, bypass), a
value of 1 means divide by 2*1 = 2, a value of ff means
divide by 2*255 = 510, and so on.
In MMC-Ver3.3-only mode, bits not implemented because
only one clock divider is supported. divide by 2*0 = 0 (no
division, bypass), value of 1 means divide by 2*1 = 2, value
of ff means divide by 2*255 = 510, and so on. In
MMC-Ver3.3-only mode, bits not implemented because
only one clock divider is supported.
Chapter 18: LPC18xx SD/MMC interface
UM10430
© NXP B.V. 2011. All rights reserved.
302 of 1164
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