LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 322
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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19.1 How to read this chapter
19.2 Basic configuration
19.3 Features
<Document ID>
User manual
The EMC is available on all LPC18xx parts.
The reset value of the EMCSTATICWAITRD0 register varies with the part revision:
For LPC1850/30/20/10 Rev ‘A’ only: The EMC supports a CCLK clock which is half of the
frequency of the BASE_M3_CLK. The EMC divided clock must be configured for
half-frequency clock operation in both the CREG6 register
CLK_EMCDIV_CFG register
The External Memory Controller is configured as follows:
Table 262. EMC clocking and power control
EMC
registers
EMC CCLK
•
•
•
•
•
•
•
•
•
•
UM10430
Chapter 19: LPC18xx External Memory Controller (EMC)
Rev. 00.13 — 20 July 2011
LPC1850/30/20/10 Rev ‘A’: Reset value of the EMCSTATICWAITRD0 register is
0x0000 000E.
LPC1850/30/20/10 Rev ‘-’: Reset value of the EMCSTATICWAITRD0 register is
0x0000 0007.
See
If the EMC CCLK is using the divided clock, the CLK_M3_EMC_DIV branch clock
must be configured for half-frequency clock operation in both the CREG6 register
(Table
The EMC is reset by the EMC_RST (reset # 21).
Delay value for address, data, and command lines can be programmed through
registers in the SCU block. (See
Dynamic chip selects each support up to 256 MB of data.
Dynamic memory interface support including Single Data Rate SDRAM.
Asynchronous static memory device support including RAM, ROM, and NOR Flash,
with or without asynchronous page mode.
Low transaction latency.
Table 262
37) and the CCU1 CLK_EMCDIV_CFG register
Base clock
BASE_M3_CLK
BASE_M3_CLK
All information provided in this document is subject to legal disclaimers.
for clocking and power control.
Rev. 00.13 — 20 July 2011
(Table
Branch clock
CLK_M3_EMC
CLK_M3_EMC_DIV
84).
Section 19.4.4
Maximum
frequency
120 MHz
120 MHz
to
Section
(Table
(Table
19.4.12.)
37) and the CCU1
Notes
-
This is the CCLK clock for
the EMC timing.
84).
© NXP B.V. 2011. All rights reserved.
User manual
322 of 1164
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