LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 654
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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26.7.9.6 MCPWM Interrupt Flags clear address
Table 566. MCPWM Interrupt Flags set address (INTF_SET - 0x400A 006C) bit description
Writing one(s) to this write-only address sets the corresponding bit(s) in INTF, thus
clearing the corresponding interrupt request(s). This is typically done in interrupt service
routines.
Table 567. MCPWM Interrupt Flags clear address (INTF_CLR - 0x400A 0070) bit description
Bit
8
9
10
14:11 -
15
31:16 -
Bit
0
1
2
3
4
5
6
7
8
9
10
14:11 -
15
31:16 -
Symbol
ILIM2_F_SET
IMAT2_F_SET
ICAP2_F_SET
ABORT_F_SET Writing a one sets the corresponding bit in the INTF register,
Symbol
ILIM0_F_CLR
IMAT0_F_CLR
ICAP0_F_CLR
-
ILIM1_F_CLR
IMAT1_F_CLR
ICAP1_F_CLR
-
ILIM2_F_CLR
IMAT2_F_CLR
ICAP2_F_CLR
ABORT_F_CLR
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.
Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.
Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.
Reserved.
thus possibly simulating hardware interrupt.
Reserved.
Writing a one clears the corresponding bit in INTEN, thus
Description
Writing a one clears the corresponding bit in the INTF register,
thus clearing the corresponding interrupt request.
Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.
Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.
Reserved.
Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.
Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.
Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.
Reserved.
Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.
Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.
Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.
Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.
disabling the interrupt.
Reserved.
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
UM10430
© NXP B.V. 2011. All rights reserved.
654 of 1164
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