LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 579

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
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User manual
1. When power is applied, the following signals are held LOW:
2. When LCD power is stabilized, a 1 is written to the LcdEn bit in the CTRL register. This
enables the following signals into their active states:
The LCDV[23:0] signals remain in an inactive state.
3. When the signals in step 2 have stabilized, the contrast voltage (not controlled or
supplied by the LCD controller) is applied to the LCD panel.
4. If required, a software or hardware timer can be used to provide the minimum display
specific delay time between application of the control signals and power to the panel
display. On completion of the time interval, power is applied to the panel by writing a 1 to
the LcdPwr bit within the CTRL register that, in turn, sets the LCDPWR signal high and
enables the LCDV[23:0] signals into their active states. The LCDPWR signal is intended
to be used to gate the power to the LCD panel.
The power-down sequence is the reverse of the above four steps and must be strictly
followed, this time, writing the respective register bits with 0.
Figure 57
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LCDLP
LCDDCLK
LCDFP
LCDENAB/ LCDM
LCDVD[23:0]
LCDLE
LCDLP
LCDDCLK
LCDFP
LCDENAB/ LCDM
LCDLE
shows the power-up and power-down sequences.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 23: LPC18xx LCD
UM10430
© NXP B.V. 2011. All rights reserved.
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