LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 340

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
19.7.20 Dynamic Memory RAS & CAS Delay registers
19.7.21 Static Memory Configuration registers
The DynamicRasCas0:3 registers enable you to program the RAS and CAS latencies for
the relevant dynamic memory. It is recommended that these registers are modified during
system initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
These registers are accessed with one wait state.
Note: The values programmed into these registers must be consistent with the values
used to initialize the SDRAM memory device.
Table 286. Dynamic Memory RASCAS Delay registers (DYNAMICRASCAS, address
The StaticConfig registers configure the static memory configuration. It is recommended
that these registers are modified during system initialization, or when there are no current
or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then
entering low-power, or disabled mode. These registers are accessed with one wait state.
Bit
1:0
7:2
9:8
31:10 -
Symbol
RAS
-
CAS
0x4000 5104 (DYNAMICRASCAS0), 0x4000 5124 (DYNAMICRASCAS1),
0x4000 5144 (DYNAMICRASCAS2), 0x4000 5164 (DYNAMICRASCAS3)) bit
description
All information provided in this document is subject to legal disclaimers.
Value Description
0x0
0x1
0x2
0x3
-
0x0
0x1
0x2
0x3
-
Rev. 00.13 — 20 July 2011
RAS latency (active to read/write delay).
Reserved.
One CCLK cycle.
Two CCLK cycles.
Three CCLK cycles (POR reset value).
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
CAS latency.
Reserved.
One CCLK cycle.
Two CCLK cycles.
Three CCLK cycles (POR reset value).
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 19: LPC18xx External Memory Controller (EMC)
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
11
-
11
-