LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 728
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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User manual
32.5.12.1 Baud rate calculation
Table 678. UART Fractional Divider Register (FDR - addresses 0x4008 1028 (UART0), 0x400C
This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of UART disabled making sure that UART is
fully software and hardware compatible with UARTs not equipped with this feature.
The UART baud rate can be calculated as:
Where UART_PCLK is the peripheral clock, DLM and DLL are the standard UART baud
rate divider registers, and DIVADDVAL and MULVAL are UART fractional baud rate
generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
The value of the FDR should not be modified while transmitting/receiving data or data may
be lost or corrupted.
If the FDR register value does not comply to these two requests, then the fractional divider
output is undefined. If DIVADDVAL is zero then the fractional divider is disabled, and the
clock will not be divided.
UART can operate with or without using the Fractional Divider. In real-life applications it is
likely that the desired baud rate can be achieved using several different Fractional Divider
settings. The following algorithm illustrates one way of finding a set of DLM, DLL,
MULVAL, and DIVADDVAL values. Such set of parameters yields a baud rate with a
relative error of less than 1.1% from the desired one.
Bit
3:0
7:4
31:8 -
1. 1 MULVAL 15
2. 0 DIVADDVAL 14
3. DIVADDVAL< MULVAL
Function
DIVADDVAL
MULVAL
1028 (UART2), 0x400C 2028 (UART3)) bit description
UART
All information provided in this document is subject to legal disclaimers.
Description
Baud rate generation pre-scaler divisor value.
If this field is 0, fractional baud rate generator will not impact the
UART baud rate.
Baud rate pre-scaler multiplier value.
This field must be greater or equal 1 for UART to operate
properly, regardless of whether the fractional baud rate
generator is used or not.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
baudrate
Rev. 00.13 — 20 July 2011
=
------------------------------------------------------------------------------------------------------------------
16
256
DLM
+
PCLK
DLL
Chapter 32: LPC18xx USART0_2_3
1
+
DivAddVal
---------------------------- -
MulVal
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
1
0
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