LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 240

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
14.4.23 SCT CTIN_6 capture input multiplexer (CTIN_6_IN)
14.4.24 SCT CTIN_7 capture input multiplexer (CTIN_7_IN)
Table 157. SCT CTIN_6 capture input multiplexer (CTIN_6_IN, address 0x400C 7058) bit
Table 158. SCT CTIN_7 capture input multiplexer (CTIN_7_IN, address 0x400C 705C) bit
Bit
0
1
2
3
7:4
31:8
Bit
0
1
2
3
7:4
Symbol
INV
EDGE
SYNCH
PULSE
SELECT
description
description
Symbol
INV
EDGE
SYNCH
PULSE
SELECT
-
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
0
1
0x0
0x1
Rev. 00.13 — 20 July 2011
Value
0
1
0
1
0
1
0
1
0x0
0x1
0x2
0x3
Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA)
Invert input
Not inverted.
Input inverted.
Enable rising edge detection
No edge detection.
Rising edge detection enabled.
Enable synchronization
Disable synchronization.
Enable synchronization.
Enable single pulse generation.
Disable single pulse generation.
Enable single pulse generation.
Select input. Values 0x4 to 0xF are reserved.
CTIN_7
U3_RXD
Description
Invert input
Not inverted.
Input inverted.
Enable rising edge detection
No edge detection.
Rising edge detection enabled.
Enable synchronization
Disable synchronization.
Enable synchronization.
Enable single pulse generation.
Disable single pulse generation.
Enable single pulse generation.
Select input. Values 0x4 to 0xF are
reserved.
CTIN_6
U3_TXD
TBD - I2S0_RX_MWS
TBD - I2S0_TX_MWS
Reserved
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
Reset value
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