LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 427
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- Current page: 427 of 1164
- Download datasheet (8Mb)
NXP Semiconductors
<Document ID>
User manual
20.10.10.1 Queue head initialization
20.10.10.2 Operational model for setup transfers
from the queue head. Therefore, software is required to track all transfer descriptors since
pointers will no longer exist within the queue head once the dTD is retired (see
Section
In addition to the current and next pointers and the dTD overlay examined in section
Operational Model For Packet Transfers, the dQH also contains the following parameters
for the associated endpoint: Multiplier, Maximum Packet Length, Interrupt On Setup. The
complete initialization of the dQH including these fields is demonstrated in the next
section.
One pair of device queue heads must be initialized for each active endpoint. To initialize a
device queue head:
Remark: The DCD must only modify dQH if the associated endpoint is not primed and
there are no outstanding dTD’s.
As discussed in section Control Endpoint Operational Model
transfer requires special treatment by the DCD. A setup transfer does not use a dTD but
instead stores the incoming data from a setup packet in an 8-byte buffer within the dQH.
Upon receiving notification of the setup packet, the DCD should handle the setup transfer
as demonstrated here:
1. Copy setup buffer contents from dQH - RX to software buffer.
2. Acknowledge setup backup by writing a “1” to the corresponding bit in
3. Check for pending data or status dTD’s from previous control transfers and flush if any
4. Decode setup packet and prepare data phase [optional] and status phase transfer as
•
•
•
•
•
Write the wMaxPacketSize field as required by the USB Chapter 9 or application
specific protocol.
Write the multiplier field to 0 for control, bulk, and interrupt endpoints. For ISO
endpoints, set the multiplier to 1,2, or 3 as required bandwidth and in conjunction with
the USB Chapter 9 protocol. Note: In FS mode, the multiplier field can only be 1 for
ISO endpoints.
Write the next dTD Terminate bit field to “1”.
Write the Halt bit in the status field to “0”.
ENDPTSETUPSTAT.
Remark: The acknowledge must occur before continuing to process the setup packet.
Remark: After the acknowledge has occurred, the DCD must not attempt to access
the setup buffer in the dQH – RX. Only the local software copy should be examined.
exist as discussed in section Flushing/De-priming an Endpoint.
Remark: It is possible for the device controller to receive setup packets before
previous control transfers complete. Existing control packets in progress must be
flushed and the new control packet completed.
require by the USB Specification Chapter 9 or application specific protocol.
Write the Active bit in the status field to “0”.
20.10.11.1).
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
(Section
20.10.8), setup
UM10430
© NXP B.V. 2011. All rights reserved.
427 of 1164
Related parts for LPC1810FET100,551
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Lpc1850/30/20/10 32-bit Arm Cortex-m3 Mcu; Up To 200 Kb Sram; Ethernet, Two High-speed Usb, Lcd, And External Memory Controller
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
NXP Semiconductors designed the LPC2458 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
NXP Semiconductors designed the LPC2468 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
NXP Semiconductors designed the LPC2470 microcontroller, powered by theARM7TDMI-S core, to be a highly integrated microcontroller for a wide range ofapplications that require advanced communications and high quality graphic displays
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
NXP Semiconductors designed the LPC2478 microcontroller, powered by theARM7TDMI-S core, to be a highly integrated microcontroller for a wide range ofapplications that require advanced communications and high quality graphic displays
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
The Philips Semiconductors XA (eXtended Architecture) family of 16-bit single-chip microcontrollers is powerful enough to easily handle the requirements of high performance embedded applications, yet inexpensive enough to compete in the market for hi
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
The Philips Semiconductors XA (eXtended Architecture) family of 16-bit single-chip microcontrollers is powerful enough to easily handle the requirements of high performance embedded applications, yet inexpensive enough to compete in the market for hi
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
The XA-S3 device is a member of Philips Semiconductors? XA(eXtended Architecture) family of high performance 16-bitsingle-chip microcontrollers
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
The NXP BlueStreak LH75401/LH75411 family consists of two low-cost 16/32-bit System-on-Chip (SoC) devices
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
The NXP LPC3141 combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2
Manufacturer:
NXP Semiconductors
Part Number:
Description:
The NXP LPC3143 combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2
Manufacturer:
NXP Semiconductors
Part Number:
Description:
The NXP LPC3152 combines an 180 MHz ARM926EJ-S CPU core, High-speed USB 2
Manufacturer:
NXP Semiconductors
Part Number:
Description:
The NXP LPC3154 combines an 180 MHz ARM926EJ-S CPU core, High-speed USB 2
Manufacturer:
NXP Semiconductors