LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 237

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
14.4.18 SCT CTIN_1 capture input multiplexer (CTIN_1_IN)
14.4.19 SCT CTIN_2 capture input multiplexer (CTIN_2_IN)
Table 151. SCT CTIN_0 capture input multiplexer (CTIN_0_IN, address 0x400C 7040) bit
Table 152. SCT CTIN_1 capture input multiplexer (CTIN_1_IN, address 0x400C 7044) bit
Table 153. SCT CTIN_2 capture input multiplexer (CTIN_2_IN, address 0x400C 7048) bit
Bit
31:8
Bit
0
1
2
3
7:4
31:8
Bit
0
1
2
3
Symbol
-
Symbol
INV
EDGE
SYNCH
PULSE
Symbol
INV
EDGE
SYNCH
PULSE
SELECT
-
description
description
description
All information provided in this document is subject to legal disclaimers.
Value
0x1
0x2
Value Description
0
1
0
1
0
1
Value Description
0
1
0
1
0
1
0
1
0x0
0x1
0x2
Rev. 00.13 — 20 July 2011
Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA)
Invert input
Not inverted.
Input inverted.
Enable rising edge detection
No edge detection.
Rising edge detection enabled.
Enable synchronization
Disable synchronization.
Enable synchronization.
Enable single pulse generation.
Description
Reserved
Reserved
Reserved
Invert input
Not inverted.
Input inverted.
Enable rising edge detection
No edge detection.
Rising edge detection enabled.
Enable synchronization
Disable synchronization.
Enable synchronization.
Enable single pulse generation.
Disable single pulse generation.
Enable single pulse generation.
Select input. Values 0x3 to 0xF are reserved.
CTIN_1
U2_TXD
Reserved
Reserved
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
Reset value
Reset value
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