LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 471
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Table 392. USB Mode register in host mode (USBMODE_H - address 0x4000 71A8) bit description
Table 393. USB Endpoint Setup Status register (ENDPTSETUPSTAT - address 0x4000 71AC) bit description
<Document ID>
User manual
Bit
4
5
31:6
Bit
3:0
31:4
Symbol Value
SDIS
VBPS
-
Symbol
ENDPT
SETUP
STAT
-
21.6.17 USB Endpoint Setup Status register (ENDPSETUPSTAT)
21.6.18 USB Endpoint Prime register (ENDPTPRIME)
0
1
0
1
-
Description
Setup endpoint status for logical endpoints.
For every setup transaction that is received, a corresponding bit in this register
is set to one. Software must clear or acknowledge the setup transfer by writing
a one to a respective bit after it has read the setup data from Queue head. The
response to a setup packet as in the order of operations and total response
time is crucial to limit bus time outs while the setup lockout mechanism is
engaged.
Reserved
For each endpoint, software should write a one to the corresponding bit whenever posting
a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin
parsing for a new transfer descriptor from the queue head and prepare a receive buffer.
Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.
Remark: These bits will be momentarily set by hardware during hardware endpoint
re-priming operations when a dTD is retired and the dQH is updated.
Description
Stream disable mode
Remark: The use of this feature substantially limits the overall USB
performance that can be achieved.
Not disabled
Disabled.
Setting to a 1 ensures that overruns/underruns of the latency FIFO are
eliminated for low bandwidth systems where the RX and TX buffers are
sufficient to contain the entire packet. Enabling stream disable also has the
effect of ensuring the the TX latency is filled to capacity before the packet is
launched onto the USB.
Note: Time duration to pre-fill the FIFO becomes significant when stream
disable is active. See TXFILLTUNING to characterize the adjustments
needed for the scheduler when using this feature.
VBUS power select
vbus_pwr_select is set LOW.
vbus_pwr_select is set HIGH
Reserved
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 21: LPC18xx USB1 Host/Device controller
Reset
value
0
-
UM10430
Reset
value
0
0
-
© NXP B.V. 2011. All rights reserved.
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