LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 674
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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27.6.2.10 QEI Velocity register
27.6.2.6 QEI Index Count register
27.6.2.7 QEI Index Compare register 0
27.6.2.8 QEI Timer Reload register
27.6.2.9 QEI Timer register
This register contains the current value of the encoder position. Increments or decrements
when encoder counts occur, depending on the direction of rotation.
Table 583. QEI Index Count register (INXCNT- address 0x400C 6020) bit description
This register contains an index compare value. This value is compared against the current
value of the index count register. Interrupts can be enabled to interrupt when the compare
value is less than, equal to, or greater than the current value of the index count register.
Table 584. QEI Index Compare register 0(INXCMP0 - address 0x400C 6024) bit description
This register contains the reload value of the velocity timer. When the timer (QEITIME)
overflows or the RESV bit is asserted, this value is loaded into the timer (QEITIME).
Table 585. QEI Timer Load register (LOAD - address 0x400C 6028) bit description
This register contains the current value of the velocity timer. When this timer overflows the
value of velocity counter (QEIVEL) is stored in the velocity capture register (QEICAP), the
velocity counter is reset to zero, the timer is reloaded with the value stored in the velocity
reload register (QEILOAD), and the velocity interrupt (TIM_Int) is asserted.
Table 586. QEI Timer register (TIME - address 0x400C 602C) bit description
This register contains the running count of velocity pulses for the current time period.
When the velocity timer (QEITIME) overflows the contents of this register is captured in
the velocity capture register (QEICAP). After capture, this register is set to zero. This
register is also reset when the velocity reset bit (RESV) is asserted.
Table 587. QEI Velocity register (VEL - address 0x400C 6030) bit description
Bit
31:0
Bit
31:0
Bit
31:0
Bit
31:0
Bit
31:0
Symbol
ENCPOS
Symbol
ICMP0
Symbol
VELLOAD
Symbol
VELVAL
Symbol
VELPC
All information provided in this document is subject to legal disclaimers.
Description
Current encoder position value.
Description
Index compare value.
Description
Current velocity timer load value.
Description
Current velocity timer value.
Description
Current velocity pulse count.
Rev. 00.13 — 20 July 2011
Chapter 27: LPC18xx Quadrature Encoder Interface (QEI)
Reset value
0xFFFF FFFF
Reset value
0xFFFF FFFF
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0
Reset value
0xFFFF FFFF
Reset value
0x0
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