LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 779
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Fig 101. SPI frame format with CPOL=0 and CPHA=0 (a) Single and b) Continuous Transfer)
a. Single transfer with CPOL=0 and CPHA=0
b. Continuous transfer with CPOL=0 and CPHA=0
SSEL
MOSI
MISO
SCK
34.7.2.1 Clock Polarity (CPOL) and Phase (CPHA) control
34.7.2.2 SPI format with CPOL=0,CPHA=0
34.7.2 SPI frame format
MSB
MSB
Both the SSP and the off-chip serial slave device then clock each data bit into their serial
shifter on the falling edge of each CLK. The received data is transferred from the serial
shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched.
The SPI interface is a four-wire interface where the SSEL signal behaves as a slave
select. The main feature of the SPI format is that the inactive state and phase of the SCK
signal are programmable through the CPOL and CPHA bits within the SSPCR0 control
register.
When the CPOL clock polarity control bit is 0, it produces a steady state low value on the
SCK pin. If the CPOL clock polarity control bit is 1, a steady state high value is placed on
the CLK pin when data is not being transferred.
The CPHA control bit selects the clock edge that captures data and allows it to change
state. It has the most impact on the first bit transmitted by either allowing or not allowing a
clock transition before the first data capture edge. When the CPHA phase control bit is 0,
data is captured on the first clock edge transition. If the CPHA clock phase control bit is 1,
data is captured on the second clock edge transition.
Single and continuous transmission signal sequences for SPI format with CPOL = 0,
CPHA = 0 are shown in
SSEL
MOSI
MISO
SCK
4 to 16 bits
All information provided in this document is subject to legal disclaimers.
MSB
Rev. 00.13 — 20 July 2011
LSB
LSB
MSB
Figure
Q
101.
4 to 16 bits
MSB
MSB
LSB
LSB
Q
4 to 16 bits
Chapter 34: LPC18xx SSP0/1
UM10430
© NXP B.V. 2011. All rights reserved.
LSB
LSB
Q
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