LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 755

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 700: Modem status interrupt generation
<Document ID>
User manual
Enable Modem Status
Interrupt (U1ER[3])
0
1
1
1
1
1
1
1
1
Fig 95. Auto-RTS Functional Timing
UART1 Rx
UART1 Rx
UART1 Rx
FIFO read
FIFO level
RTS1 pin
33.5.9.2 Auto-CTS
start
N-1
byte N
Example: Suppose the UART1 operating in ‘550 mode has trigger level in U1FCR set to
0x2 then if Auto-RTS is enabled the UART1 will de-assert the RTS1 output as soon as the
receive FIFO contains 8 bytes
reasserted as soon as the receive FIFO hits the previous trigger level: 4 bytes.
The Auto-CTS function is enabled by setting the CTSen bit. If Auto-CTS is enabled the
transmitter circuitry in the U1TSR module checks CTS1 input before sending the next
data byte. When CTS1 is active (low), the transmitter sends the next byte. To stop the
transmitter from sending the following byte, CTS1 must be released before the middle of
the last stop bit that is currently being sent. In Auto-CTS mode a change of the CTS1
signal does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set,
Delta CTS bit in the U1MSR will be set though.
generating a Modem Status interrupt.
The auto-CTS function reduces interrupts to the host system. When flow control is
enabled, a CTS1 state change does not trigger host interrupts because the device
automatically controls its own transmitter. Without Auto-CTS, the transmitter sends any
data present in the transmit FIFO and a receiver overrun error can result.
illustrates the Auto-CTS functional timing.
CTSen
(U1MCR[7])
x
0
0
0
1
1
1
1
1
stop
start
N
CTS Interrupt
Enable (U1IER[7])
x
x
x
x
0
0
1
1
1
All information provided in this document is subject to legal disclaimers.
bits0..7
N-1
Rev. 00.13 — 20 July 2011
stop
N-2
(Table 697 on page
Delta CTS
(U1MSR[0])
x
0
1
x
x
x
0
1
x
N-1
N-2
Delta DCD or Trailing Edge RI
or Delta DSR (U1MSR[3] or
U1MSR[2] or U1MSR[1])
x
0
x
1
0
1
0
x
1
Table 700
751). The RTS1 output will be
M+2
lists the conditions for
Chapter 33: LPC18xx UART1
M+1
M
start
UM10430
© NXP B.V. 2011. All rights reserved.
Figure 96
bits0..7
Modem Status
Interrupt
No
No
Yes
Yes
No
Yes
No
Yes
Yes
M-1
755 of 1164
stop