LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 205

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LPC1810FET100,551

Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr

Specifications of LPC1810FET100,551

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
NXP Semiconductors
<Document ID>
User manual
13.4.2 Pin configuration registers for high drive pins
Table 111. Pin configuration for normal drive pins P0_n to PF_n and CLK0 to CLK3 registers
Each digital pin and each clock pin on the LPC18xx have an associated pin configuration
register which determines the pin’s function and electrical characteristics. The assigned
functions for each pin are listed in
Bit
2:0
3
4
5
6
31:7
Symbol
MODE
EPD
EPUN
EHS
EZI
-
(SFS, address 0x4008 6000 (SPSP0_0) to 0x4008 6C0C (SFSCLK3)) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0
1
0
1
0
1
0
1
Description
Select pin function
Function 0 (default)
Function 1
Function 2
Function 3
Function 4
Function 5
Function 6
Function 7
Enable pull-down resistor at pad
Disable pull-down.
Enable pull-down.
Disable pull-up resistor at pad. By default,
the pull-up resistor is enabled at reset.
Enable pull-up
Disable pull-up
Slew rate
Slow
Fast
Input buffer enable. The input buffer is
disabled by default at reset and must be
enabled for receiving.
Disable input buffer
Enable input buffer
Reserved
Table
Chapter 13: LPC18xx System Control Unit (SCU)
109.
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
-
205 of 1164
Access
R/W
R/W
R/W
R/W
R/W
-

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