NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 840

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

Table 161.
840
Ultra ATA Timing (Mode 3, Mode 4, Mode 5) (Sheet 2 of 2) (Mobile Only)
NOTES:
1.
2.
Sym
t92b
t96a
t96b
t98a
t98b
t93
t94
t95
t97
t99
The specification symbols in parentheses correspond to the AT Attachment
Interface (ATA/ATAPI
See the AT Attachment
details on measuring these timing parameters.
CRC Word Hold Time at
Sender
CRC word valid hold
time at sender (from
DMACK# negation until
CRC may become
invalid) (see Note 2)
(Tcvh)
STROBE output
released-to-driving to
the first transition of
critical timing (Tzfs)
Data Output Released-
to-Driving Until the First
Transition of Critical
Timing (Tdzfs)
Unlimited Interlock Time
(Tui)
Maximum time allowed
for output drivers to
release (from asserted
or negated) (Taz)
Drivers to assert or
negate (from released)
(Tzad)
Ready-to-final-STROBE
time (no STROBE edges
shall be sent this long
after negation of
DMARDY#) (Trfs)
Maximum time before
releasing IORDY
(Tiordyz)
Minimum time before
driving IORDY (see Note
2) (Tziordy)
Time from STROBE edge
to negation of DMARQ or
assertion of STOP (when
sender terminates a
burst) (Tss)
Parameter (1)
–
6) specification name.
–
6 with Packet Interface (ATA/ATAPI
Min
6.2
20.
50
—
—
—
Mode 3
0
0
0
0
0
(ns)
Max
10
60
20
—
—
—
—
—
—
—
Min
6.2
6.7
50
—
—
—
Mode 4
0
0
0
0
(ns)
Max
10
60
20
—
—
—
—
—
—
—
Min
10.
35
25
50
—
—
—
Mode 5
0
0
0
0
(ns)
–
Max
10
50
20
—
—
—
—
—
—
—
6) specification for further
Intel
Electrical Characteristics
Measuring
See Note 2
®
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Location
Sender
Sender
Sender
ICH8 Family Datasheet
Device
Device
Device
Device
Host
Host
–
6 with Packet
Figure
33
32