NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 17

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

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Intel
®
ICH8 Family Datasheet
11.2
SATA Controller Registers (D31:F2)....................................................................... 465
12.1
11.1.7 SCC—Sub Class Code Register (IDE—D31:F1).......................................... 451
11.1.8 BCC—Base Class Code Register (IDE—D31:F1) ........................................ 452
11.1.9 CLS—Cache Line Size Register (IDE—D31:F1) .......................................... 452
11.1.10PMLT—Primary Master Latency Timer Register (IDE—D31:F1) .................... 452
11.1.11PCMD_BAR—Primary Command Block Base Address
11.1.12PCNL_BAR—Primary Control Block Base Address
11.1.13SCMD_BAR—Secondary Command Block Base Address
11.1.14SCNL_BAR—Secondary Control Block Base Address
11.1.15BM_BASE — Bus Master Base Address Register
11.1.16IDE_SVID — Subsystem Vendor Identification
11.1.17IDE_SID — Subsystem Identification Register
11.1.18INTR_LN—Interrupt Line Register (IDE—D31:F1)...................................... 455
11.1.19INTR_PN—Interrupt Pin Register (IDE—D31:F1) ....................................... 455
11.1.20IDE_TIMP — IDE Primary Timing Register (IDE—D31:F1) .......................... 455
11.1.21IDE_TIMS — IDE Secondary Timing Register
11.1.22SLV_IDETIM—Slave (Drive 1) IDE Timing Register
11.1.23SDMA_CNT—Synchronous DMA Control Register
11.1.24SDMA_TIM—Synchronous DMA Timing Register
11.1.25IDE_CONFIG—IDE I/O Configuration Register
11.1.26ATC—APM Trapping Control Register (IDE—D31:F1) ................................. 461
11.1.27ATS—APM Trapping Status Register (IDE—D31:F1)................................... 461
Bus Master IDE I/O Registers (IDE—D31:F1) ...................................................... 462
11.2.1 BMICP—Bus Master IDE Command Register
11.2.2 BMISP—Bus Master IDE Status Register (IDE—D31:F1) ............................. 463
11.2.3 BMIDP—Bus Master IDE Descriptor Table Pointer Register
PCI Configuration Registers (SATA–D31:F2)........................................................ 465
12.1.1 VID—Vendor Identification Register (SATA—D31:F2) ................................ 466
12.1.2 DID—Device Identification Register (SATA—D31:F2) ................................. 467
12.1.3 PCICMD—PCI Command Register (SATA–D31:F2)..................................... 467
12.1.4 PCISTS — PCI Status Register (SATA–D31:F2) ......................................... 468
12.1.5 RID—Revision Identification Register (SATA—D31:F2)............................... 468
12.1.6 PI—Programming Interface Register (SATA–D31:F2)................................. 469
12.1.7 SCC—Sub Class Code Register (SATA–D31:F2) ........................................ 470
12.1.8 BCC—Base Class Code Register
Register (IDE—D31:F1)......................................................................... 452
Register (IDE—D31:F1)......................................................................... 453
Register (IDE D31:F1) .......................................................................... 453
Register (IDE D31:F1) .......................................................................... 453
(IDE—D31:F1) ..................................................................................... 454
(IDE—D31:F1) ..................................................................................... 454
(IDE—D31:F1) ..................................................................................... 454
(IDE—D31:F1) ..................................................................................... 457
(IDE—D31:F1) ..................................................................................... 457
(IDE—D31:F1) ..................................................................................... 458
(IDE—D31:F1) ..................................................................................... 459
(IDE—D31:F1) ..................................................................................... 460
(IDE—D31:F1) ..................................................................................... 462
(IDE—D31:F1) ..................................................................................... 463
12.1.6.1 When Sub Class Code Register
12.1.6.2 When Sub Class Code Register
12.1.6.3 When Sub Class Code Register
(SATA–D31:F2SATA–D31:F2) ................................................................ 470
(D31:F2:Offset 0Ah) = 01h ...................................................... 469
(D31:F2:Offset 0Ah) = 04h ...................................................... 469
(D31:F2:Offset 0Ah) = 06h ...................................................... 470
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