NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 140

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

5.8.1
5.8.1.1
Table 51.
5.8.1.2
Table 52.
140
Interrupt Handling
Generating Interrupts
The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each
interrupt level. These bits are used to determine the interrupt vector returned, and
status of any other pending interrupts.
Interrupt Status Registers
Acknowledging Interrupts
The processor generates an interrupt acknowledge cycle that is translated by the host
bridge into a PCI Interrupt Acknowledge Cycle to the ICH8. The PIC translates this
command into two internal INTA# pulses expected by the 8259 cores. The PIC uses the
first internal INTA# pulse to freeze the state of the interrupts for priority resolution. On
the second INTA# pulse, the master or slave sends the interrupt vector to the
processor with the acknowledged interrupt code. This code is based upon bits [7:3] of
the corresponding ICW2 register, combined with three bits representing the interrupt
within that controller.
Content of Interrupt Vector Byte
IMR
Master, Slave Interrupt
IRR
ISR
Bit
Interrupt Request Register. This bit is set on a low to high transition of the interrupt
line in edge mode, and by an active high level in level mode. This bit is set whether or
not the interrupt is masked. However, a masked interrupt will not generate INTR.
Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared,
when an interrupt acknowledge cycle is seen, and the vector returned is for that
interrupt.
Interrupt Mask Register. This bit determines whether an interrupt is masked.
Masked interrupts will not generate INTR.
IRQ7,15
IRQ6,14
IRQ5,13
IRQ4,12
IRQ3,11
IRQ2,10
IRQ1,9
IRQ0,8
Bits [7:3]
ICW2[7:3]
Table 51
Description
defines the IRR, ISR, and IMR.
Bits [2:0]
111
110
101
100
011
010
001
000
Intel
®
Functional Description
ICH8 Family Datasheet