NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 239

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.21.1.2
Intel
®
ICH8 Family Datasheet
Exiting D3/CRST# when Docked
10. HD Audio Bus Driver software “discovers” the dock codecs by comparing the bits
6. After the controller asserts HDA_DOCK_EN# it waits for a minimum of 2400 BCLKs
7. The Connect/Turnaround/Address Frame hardware initialization sequence will now
8. After this hardware initialization sequence is complete (approximately 32 frames),
9. Alternatively to step #8, the HD Audio Bus Driver may choose to enable an
1. In D3/CRST#, CRST# is asserted by the HD Audio Bus Driver. CRST# asserted
2. The Bus Driver clears the STATESTS bits, then de-asserts CRST#, waits
3. When CRST# is de-asserted, the dock state machine detects that DCKCTL.DA is
4. The Bus Driver enumerates the codecs present as indicated via the STATESTS bits.
5. Note that this process did not require BIOS or ACPI BIOS to set the DCKCTL.DA bit.
glitches on these signals. Note that in the ICH8 the first 8 bits of the Command field
are “reserved” and always driven to 0s. This creates a predictable point in time to
always assert HDA_DOCK_EN#. Note that the HD Audio link reset exit specification
that requires that SYNC and SDO be driven low during BCLK startup is not assured.
Note also that the SDO and BCLK signals may not be low while HDA_DOCK_RST#
is asserted which also violates the spec.
(100 us) and then de-asserts HDA_DOCK_RST#. This is done in such a way to
meet the HD Audio link reset exit specification. HDA_DOCK_RST# de-assertion
should be synchronous to BCLK and timed such that there are least 4 full BCLKS
from the de-assertion of HDA_DOCK_RST# to the first frame SYNC assertion.
occur on the dock codecs' SDI signals. A dock codec is detected when SDI is high
on the last BCLK cycle of the Frame Sync of a Connect Frame. The appropriate
bit(s) in the State Change Status (STATESTS) register will be set. The Turnaround
and Address Frame initialization sequence then occurs on the dock codecs' SDI(s).
the controller hardware sets the DCKSTS.DM bit to 1 indicating that the dock is now
mated. ACPI BIOS polls the DCKSTS.DM bit and when it detects it is set to 1,
conveys this to the OS through a plug-N-play IRP. This eventually invokes the HD
Audio Bus Driver, which then begins it's codec discovery, enumeration, and
configuration process.
interrupt by setting the WAKEEN bits for SDINs that didn't originally have codecs
attached to them. When a corresponding STATESTS bit gets set an interrupt will be
generated. In this case the HD Audio Bus Driver is called directly by this interrupt
instead of being notified by the plug-N-play IRP.
now set in the STATESTS register with the bits that were set prior to the docking
event.
resets the dock state machines, but does not reset the DCKCTL.DA bit. Because the
dock state machines are reset, the dock is electrically isolated (HDA_DOCK_EN#
de-asserted) and DOCK_RST# is asserted.
approximately 7ms, then checks the STATESTS bits to see which codecs are
present.
still set and the controller hardware sequences through steps to electrically connect
the dock by asserting HDA_DOCK_EN# and then eventually de-asserts
DOCK_RST#. This completes within the 7 ms mentioned in step 2).
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