NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 691
NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
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Intel
17.2.38
17.2.39
Intel
®
®
ICH8 Family Datasheet
High Definition Audio Controller Registers (D27:F0)
SDLPIB—Stream Descriptor Link Position in Buffer
Register (Intel
Memory Address:Input Stream[0]: HDBAR + 84h
Default Value:
SDCBL—Stream Descriptor Cyclic Buffer Length Register
(Intel
Memory Address:Input Stream[0]: HDBAR + 88h
Default Value:
31:0
31:0
Bit
Bit
Link Position in Buffer — RO. This field indicates the number of bytes that have been
received off the link. This register will count from 0 to the value in the Cyclic Buffer
Length register and then wrap to 0.
Cyclic Buffer Length — R/W. This field indicates the number of bytes in the complete
cyclic buffer. This register represents an integer number of samples. Link Position in
Buffer will be reset when it reaches this value.
Software may only write to this register after Global Reset, Controller Reset, or Stream
Reset has occurred. This value should be only modified when the RUN bit is 0. Once the
RUN bit has been set to enable the engine, software must not write to this register until
after the next reset is asserted, or transfer may be corrupted.
®
High Definition Audio Controller—D27:F0)
Input Stream[1]: HDBAR + A4h
Input Stream[2]: HDBAR + C4h
Input Stream[3]: HDBAR + E4h
Output Stream[0]: HDBAR + 104h
Output Stream[1]: HDBAR + 124h
Output Stream[2]: HDBAR + 144h
Output Stream[3]: HDBAR + 164h
00000000h
Input Stream[1]: HDBAR + A8h
Input Stream[2]: HDBAR + C8h
Input Stream[3]: HDBAR + E8h
Output Stream[0]: HDBAR + 108h
Output Stream[1]: HDBAR + 128h
Output Stream[2]: HDBAR + 148h
Output Stream[3]: HDBAR + 168h
00000000h
®
High Definition Audio Controller—D27:F0)
Description
Description
Size:
Attribute:
Attribute:
Size:
32 bits
R/W
RO
32 bits
691
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