NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 83

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

Signal Description
2.23
Table 27.
2.24
Table 28.
Intel
®
ICH8 Family Datasheet
GPIO[47:44]
GPIO[43:40]
Intel
Intel
General Purpose I/O Signals
General Purpose I/O Signals (Sheet 1 of 3)
TACH0/GPIO17
GPIO55
GPIO54
GPIO53
GPIO52
GPIO51
GPIO50
GPIO49
GPIO48
GPIO39
GPIO38
TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
Name
PWM[2:0]
®
Name
PECI
SST
Quiet System Technology Signals
®
Quiet System Technology (Desktop Only)
Type
N/A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Type
I/O
I/O
OD
Tolerance
V_CPU_IO
I
3.3 V
5.5 V
3.3 V
5.5 V
3.3 V
5.5 V
3.3 V
3.3 V
3.3 V
3.3V
N/A
Fan Pulse Width Modulation Outputs: This is a Pulse Width
Modulated duty cycle output signal that is used Intel Quiet
System Technology.
When controlling a 3-wire fan, this signal controls a power
transistor that, in turn, controls power to the fan. When
controlling a 4-wire fan, this signal is connected to the “Control”
signal on the fan. The polarity of this signal is programmable.
The output default is low. These signals are 5 V tolerant.
Fan Tachometer Inputs: These are Tachometer pulse input
signals that are used to measure fan speed. The signals are
connected to the “Sense” signal on the fan.
Can instead be used as a GPIO signal.
Simple Serial Transport: Single-wire, serial bus. Connect to
SST compliant devices such as SST thermal sensors or voltage
sensors.
Platform Environmental Control Interface: Single-wire,
serial bus. This signal connects to the corresponding pin of the
processor for accessing processor digital thermometer.
V_CPU_IO
Resume
Power
Well
Core
Core
Core
Core
Core
Core
Core
Core
Core
N/A
Default
Native
Native
Native
Native
Native
Native
Native
Native
N/A
GPI
GPI
GPI
Description
Multiplexed with GNT3#
Multiplexed with REQ3#
(Note 5)
Multiplexed with GNT2#
Multiplexed with REQ2#
(Note 5)
Multiplexed with GNT1#
Multiplexed with REQ1#
(Note 5)
Multiplexed with CPUPWRGD
(Note 4)
Multiplexed with SDATAOUT1
Not implemented.
Multiplexed with OC[4:1]#
(Note 5)
Multiplexed with SDATAOUT0
Multiplexed with SLOAD
Description
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