NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 451

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

IDE Controller Registers (D31:F1) (Mobile Only)
11.1.5
11.1.6
11.1.7
Intel
®
ICH8 Family Datasheet
RID—Revision Identification Register (IDE—D31:F1)
Offset Address:
Default Value:
PI—Programming Interface Register (IDE—D31:F1)
Address Offset:
Default Value:
SCC—Sub Class Code Register (IDE—D31:F1)
Address Offset:
Default Value:
7:0
6:4
7:0
Bit
Bit
Bit
7
3
2
1
0
Revision ID — RO. Refer to the Intel
Update for the value of the Revision ID Register
This read-only bit is a 1 to indicate that the ICH8M supports bus master operation
Reserved. Hardwired to 000b.
SOP_MODE_CAP — RO. This read-only bit is a 1 to indicate that the secondary
controller supports both legacy and native modes.
SOP_MODE_SEL — R/W. This read/write bit determines the mode that the secondary
IDE channel is operating in.
0 = Legacy-PCI mode (default)
1 = Native-PCI mode
POP_MODE_CAP — RO. This read-only bit is a 1 to indicate that the primary controller
supports both legacy and native modes.
POP_MODE_SEL — R/W. This read/write bits determines the mode that the primary
IDE channel is operating in.
0 = Legacy-PCI mode (default)
1 = Native-PCI mode
Sub Class Code (SCC) — RO.
01h = IDE device, in the context of a mass storage device.
08h
See bit description
09h
8Ah
0Ah
01h
®
Description
Description
Description
I/O Controller Hub 8 (ICH8) Family Specification
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO, R/W
RO
8 bits
8 bits
8 bits
RO
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