NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 671

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

Intel
17.2.4
17.2.5
Intel
®
®
ICH8 Family Datasheet
High Definition Audio Controller Registers (D27:F0)
OUTPAY—Output Payload Capability Register
(Intel
Memory Address:HDBAR + 04h
Default Value:
INPAY—Input Payload Capability Register
(Intel
Memory Address:HDBAR + 06h
Default Value:
15:7
15:7
6:0
6:0
Bit
Bit
Reserved.
Output Payload Capability — RO. Hardwired to 3Ch indicating 60 word payload.
This field indicates the total output payload available on the link. This does not include
bandwidth used for command and control. This measurement is in 16-bit word
quantities per 48 MHz frame. The default link clock of 24.000 MHz (the data is double
pumped) provides 1000 bits per frame, or 62.5 words in total. 40 bits are used for
command and control, leaving 60 words available for data payload.
00h = 0 word
01h = 1 word payload.
.....
FFh = 256 word payload.
Reserved.
Input Payload Capability — RO. Hardwired to 1Dh indicating 29 word payload.
This field indicates the total output payload available on the link. This does not include
bandwidth used for response. This measurement is in 16-bit word quantities per 48
MHz frame. The default link clock of 24.000 MHz provides 500 bits per frame, or
31.25 words in total. 36 bits are used for response, leaving 29 words available for data
payload.
00h = 0 word
01h = 1 word payload.
.....
FFh = 256 word payload.
®
®
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
003Ch
001Dh
Description
Description
Attribute:
Size:
Attribute:
Size:
RO
16 bits
RO
16 bits
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