NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 232

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

5.20.5
5.20.6
5.20.7
Note:
Note:
232
SMBALERT#
SMBALERT# is multiplexed with GPIO[11]. When enable and the signal is asserted, The
ICH8 can generate an interrupt, an SMI#, or a wake event from S1–S5.
SMBus CRC Generation and Checking
If the AAC bit is set in the Auxiliary Control register, the ICH8 automatically calculates
and drives CRC at the end of the transmitted packet for write cycles, and will check the
CRC for read cycles. It will not transmit the contents of the PEC register for CRC. The
PEC bit must not be set in the Host Control register if this bit is set, or unspecified
behavior will result.
If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the
Auxiliary Status register at offset 0Ch will be set.
SMBus Slave Interface
The ICH8’s SMBus Slave interface is accessed via the SMBus. The SMBus slave logic will
not generate or handle receiving the PEC byte and will only act as a Legacy Alerting
Protocol device. The slave interface allows the ICH8 to decode cycles, and allows an
external microcontroller to perform specific actions. Key features and capabilities
include:
The external microcontroller should not attempt to access the Intel ICH8’s SMBus slave
logic until either:
If a master leaves the clock and data bits of the SMBus interface at 1 for 50 µs or more
in the middle of a cycle, the ICH8 slave logic's behavior is undefined. This is interpreted
as an unexpected idle and should be avoided when performing management activities
to the slave logic.
When an external microcontroller accesses the SMBus Slave Interface over the SMBus
a translation in the address is needed to accommodate the least significant bit used for
read/write control. For example, if the ICH8 slave address (RCV_SLVA) is left at 44h
(default), the external micro controller would use an address of 88h/89h (write/read).
• Supports decode of three types of messages: Byte Write, Byte Read, and Host
• Receive Slave Address register: This is the address that the ICH8 decodes. A
• Receive Slave Data register in the SMBus I/O space that includes the data written
• Registers that the external microcontroller can read to get the state of the ICH8.
• Status bits to indicate that the SMBus slave logic caused an interrupt or SMI# due
Notify.
default value is provided so that the slave interface can be used without the
processor having to program this register.
by the external microcontroller.
to the reception of a message that matched the slave address.
— Bit 0 of the Slave Status Register for the Host Notify command
— Bit 16 of the SMI Status Register
— 800 milliseconds after both: RTCRST## is high and RSMRST# is high, OR
— the PLTRST# de-asserts
— The 800 ms case is based on the scenario where the RTC Battery is dead or
missing such that the RTC Power Well comes up simultaneously with Suspend
Well. In this case, the RTC clock may take a while to stabilize. The ICH8 uses
the RTC clock to extend the internal RSMRST# by ~100 ms. Therefore, if the
clock is slow to toggle, this time could be extended. 800 ms is assumed to be
sufficient guardband for this.
(Section
9.8.3.15) for all others
Intel
®
Functional Description
ICH8 Family Datasheet