NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 599
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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EHCI Controller Registers (D29:F7, D26:F7)
Intel
®
ICH8 Family Datasheet
12:6
Bit
15
14
13
5
4
3
2
1
0
SMI on BAR Enable — R/W.
0 = Disable.
1 = Enable. When this bit is 1 and SMI on BAR (D29:F7, D26:F7:6Ch, bit 31) is 1, then
SMI on PCI Command Enable — R/W.
0 = Disable.
1 = Enable. When this bit is 1 and SMI on PCI Command (D29:F7, D26:F7:6Ch, bit 30)
SMI on OS Ownership Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1 AND the OS Ownership Change bit (D29:F7,
Reserved — RO. Hardwired to 00h
SMI on Async Advance Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Async Advance bit (D29:F7,
SMI on Host System Error Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Host System Error (D29:F7,
SMI on Frame List Rollover Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Frame List Rollover bit (D29:F7,
SMI on Port Change Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Port Change Detect bit (D29:F7,
SMI on USB Error Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on USB Error bit (D29:F7, D26:F7:6Ch,
SMI on USB Complete Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on USB Complete bit (D29:F7,
the host controller will issue an SMI.
is 1, then the host controller will issue an SMI.
D26:F7:6Ch, bit 29) is 1, the host controller will issue an SMI.
D26:F7:6Ch, bit 21) is a 1, the host controller will issue an SMI immediately.
D26:F7:6Ch, bit 20) is a 1, the host controller will issue an SMI.
D26:F7:6Ch, bit 19) is a 1, the host controller will issue an SMI.
D26:F7:6Ch, bit 18) is a 1, the host controller will issue an SMI.
bit 17) is a 1, the host controller will issue an SMI immediately.
D26:F7:6Ch, bit 16) is a 1, the host controller will issue an SMI immediately.
Description
599
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