NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 328
NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
- Current page: 328 of 890
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9.1.11
9.1.12
328
SS—Sub System Identifiers Register (LPC I/F—D31:F0)
Offset Address: 2Ch
Default Value:
This register is initialized to logic 0 by the assertion of PLTRST#. This register can be
written only once after PLTRST# de-assertion.
PMBASE—ACPI Base Address Register (LPC I/F—D31:F0)
Offset Address: 40h
Default Value:
Lockable:
Sets base address for ACPI I/O registers, GPIO registers and TCO I/O registers. These
registers can be mapped anywhere in the 64-K I/O space on 128-byte boundaries.
31:16
15:0
31:16
Bit
15:7
6:1
Bit
0
Subsystem ID (SSID) — R/WO This is written by BIOS. No hardware action taken on
this value.
Subsystem Vendor ID (SSVID) — R/WO This is written by BIOS. No hardware action
taken on this value.
Reserved
Base Address — R/W. This field provides 128 bytes of I/O space for ACPI, GPIO, and
TCO logic. This is placed on a 128-byte boundary.
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate I/O space.
00000000h
00000001h
No
–
–
43h
2Fh
Description
Description
Attribute:
Size:
Attribute:
Size:
Usage:
Power Well:
LPC Interface Bridge Registers (D31:F0)
R/WO
32 bits
R/W, RO
32 bit
ACPI, Legacy
Core
Intel
®
ICH8 Family Datasheet
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